3.3 Clocking Structure

The following figure shows the clocking structure of the PolarFire USXGMII design and consists of the following clock domains:

  • On-chip 160 MHz RC Oscillator: Drives PF_XCVR_ERM_C0:XCVR_CTRL_CLK
  • PF_XCVR_REF_CLK_C0: Generates reference clock required for the PF_DRI_C0 block
  • PF_XCVR_REF_CLK_1: Generates reference clocks required for:
    • Driving Transceiver CDR reference clock used to derive the RX clocks for Transceiver, USXGMII, and Core10GMAC blocks.
    • Driving TX clocks for USXGMII and Core10GMAC blocks.
Figure 3-4. Clocking Structure