3 Demo Design Architecture

The following figure shows the architecture of the demo design.

Figure 3-1. USXGMII Design Architecture

The design loops back the XGMII traffic generated by the test module as per the following steps:

  1. The data generated by the test module passes through the Aquantia PHY (AQR107) and is received by the PolarFire transceiver inside the FPGA through FMC.
  2. The PolarFire transceiver RX converts the serial data stream into parallel data and clock, which is sent to the CoreUSXGMII RX interface. The data is downscaled at the CoreUSXGMII RX interface based on the data-rate set during Auto-Negotiation.
  3. CoreUSXGMII RX sends the data to the Ethernet MAC RX (Core10GMAC), which loops back the XGMII data and RX control signals using a FIFO logic implemented in RTL.
  4. The looped back data passes through Core10GMAC TX, CoreUSXGMII TX (data upscaling), PF_XCVR TX, and the Aquantia PHY, and received by the test module.
  5. The received packets are analyzed for throughput rate and errors using the test module software.