3.4 Reset Structure

The Reset structure is implemented in the Clock_Reset_Subsystem SmartDesign file in the Libero design. This SmartDesign module generates the following reset signals:

• FABRIC_RESET_N: To reset the Mi-V_Subsystem. FABRIC_RESET_N is asserted when the SYSRESET_N, PHY_RST_OUT, DEVICE_INIT_DONE, and PLL_LOCK signals are asserted. PHY_RST_OUT is asserted when the external PHY is powered up.
• XCVR_PCS_PMA_RESET and PHY_RST: To reset the PolarFire Transceiver (PF_XCVR_ERM) PMA and PCS. XCVR_PCS_PMA_RESET and PHY_RST are asserted when SYSRESETN and DEVICE_INIT_DONE signals are asserted.

The Mi-V Subsystem generates the following reset signals after reset:

• EXT_RST: To reset FIFO, USXGMII blocks.
• MAC_RST: To reset Core10GMAC block using the CoreGPIO APB interface.