3.1 I/O Ports

The following table lists the important I/O ports of the USXGMII Libero hardware design.

Table 3-1. I/O Ports
Port Name	Direction	Description
TMS	Input	JTAG signals interfaced to the Mi-V soft processor for debugging
TRSTB	Input
TDI	Input
TCK	Input
TDO	Output
REF_CLK_PAD_P_0	Input	148.5 MHz reference clock received from the on-board LVDS oscillator. This reference clock is used to generate clocks for the fabric and DRI interface.
REF_CLK_PAD_N_0	Input
PHY_RSTN_OUT	Input	Active-high reset signal from external PHY. This signal indicates that the external PHY is powered-up.
LANE0_RXD_P	Input	Receive lane of the Transceiver to receive the serial data through the FMC from the external PHY. These pads are connected to the receive pins of the FMC.
LANE0_RXD_N	Input
LANE0_TXD_P	Output	Transmit lane of the Transceiver to transmit the serial data through the FMC to the external PHY. These pads are connected to the transmit pins Transceiver.
LANE0_TXD_N	Output
REF_CLK_PAD_P	Input	Reference clocks received from the external PHY card
REF_CLK_PAD_N	Input	Reference clocks received from the external PHY card
SYSRESTN	Input	Active-low system reset. Asserted by pressing the on-board AL27 push button.
TX	Input	UART interface to the FPGA from the Host PC
RX	Output	UART interface to the Host PC from the FPGA
PHY_MDIO	Input/Output	Management Data IO Interface for accessing the external PHY registers
PHY_MDC	Output	Management Data IO clock fed to the external PHY
PHY_RST	Output	Active-high reset signal to the external PHY

AN5488