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PolarFire FPGA USXGMII Design AN5488
PolarFire FPGA USXGMII Design AN5488
  1. Home
  2. 3 Demo Design Architecture
  3. 3.2 Subsystem Components
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AN5488

  • PolarFire FPGA USXGMII Design
  • 1 Demo Requirements
  • 2 Prerequisites
  • 3 Demo Design Architecture
    • 3.1 I/O Ports
    • 3.2 Subsystem Components
      • 3.2.1 Core10GMAC
      • 3.2.2 CoreUSXGMII
      • 3.2.3 PF_XCVR_ERM
      • 3.2.4 Mi-V Processor Subsystem
      • 3.2.5 FIFO Logic
      • 3.2.6 PF_TX_PLL
      • 3.2.7 PF_XCVR_REF_CLK
      • 3.2.8 PF_CCC
      • 3.2.9 PF_INIT_MONITOR
    • 3.3 Clocking Structure
    • 3.4 Reset Structure
    • 3.5 Resource Utilization
  • 4 Setting Up the Demo
  • 5 Running the Demo
  • 6 Appendix A: Running the Tcl Script
  • 7 Revision History
  • Microchip FPGA Support
  • Microchip Information

3.2 Subsystem Components

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The following sections describe the subsystems used in the design:

  • Core10GMAC
  • CoreUSXGMII
  • PF_XCVR_ERM
  • Mi-V Processor Subsystem
  • FIFO Logic
  • PF_TX_PLL
  • PF_XCVR_REF_CLK
  • PF_CCC

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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