2.3 Pin Details
The following table describes the ATA8352 module pin details. Refer to Figure 2-1 for the signal names.
| Name | Description |
|---|---|
| ENA | (Optional) Active high input to enable the DC/DC converter for 1.25V supply |
| GND | GND connection |
| VDD_1V2 | 1.25V supply connection (use either external 1.25V supply or the on-module DCDC converter if mounted. Do not use both supplies.) |
| GND | GND connection |
| VDD_IO | 3.3V IO supply connection |
| GND | GND connection |
| MST-CLK | 4 MHz master clock output from the ATA8352 |
| N-RST | Active low reset input signal for the ATA8352 |
| SPI-CLK | SPI clock input signal for the ATA8352 |
| SPI-CE | Active high SPI chip enable signal for the ATA8352 |
| SPI-MISO | SPI MISO input signal for the ATA8352 |
| SPI-MOSI | SPI MOSl output signal from the ATA8352 |
| GPO-4 | GPO4 signal from the ATA8352 |
| GPO-3 | GPO3 signal from the ATA8352 |
| GPO-2 | GPO2 signal from the ATA8352 |
| GPO-1 | GPO1 signal from the ATA8352 |
| GPO-0 | GPO0 signal from the ATA8352 |
| GND | GND connection |
| IRQ | Active high interrupt output from the ATA8352 |
| 48M | 48 MHz input clock |
| RF | SMA 50Ω antenna connector footprint |
| SYNC | Synchronization input signal |