19.7.2 Timer1 Gate Source Selection

The gate source for Timer1 is selected using the GSS bits. The polarity selection for the gate source is controlled by the GPOL bit. The table below lists the gate source selections.

Table 19-4. Timer Gate Signal Selection
GSSGate Source
Timer1Timer3Timer5
1111ReservedReservedReserved
1110ZCDOUTZCDOUTZCDOUT
1101CMP2OUTCMP2OUTCMP2OUT
1100CMP1OUTCMP1OUTCMP1OUT
1011PWM4OUTPWM4OUTPWM4OUT
1010PWM3OUTPWM3OUTPWM3OUT
1001CCP2OUTCCP2OUTCCP2OUT
1000CCP1OUTCCP1OUTCCP1OUT
0111TMR6OUT (post-scaled)TMR6OUT (post-scaled)TMR6OUT (post-scaled)
0110TMR5 overflowTMR5 overflowReserved
0101TMR4OUT (post-scaled)TMR4OUT (post-scaled)TMR4OUT (post-scaled)
0100TMR3 overflowReservedTMR3 overflow
0011TMR2OUT (post-scaled)TMR2OUT (post-scaled)TMR2OUT (post-scaled)
0010ReservedTMR1 overflowTMR1 overflow
0001TMR0 overflowTMR0 overflowTMR0 overflow
0000Pin selected by T1GPPSPin selected by T3GPPSPin selected by T5GPPS

Any of the above mentioned signals can be used to trigger the gate. The output of the CMPx can be synchronized to the Timer1 clock or left asynchronous. For more information refer to the Comparator Output Synchronization section.