19.13 Register Summary - Timer1
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x0FC0 | Reserved | |||||||||
| 0x0FC1 | TMR5 | 7:0 | TMRxL[7:0] | |||||||
| 15:8 | TMRxH[7:0] | |||||||||
| 0x0FC3 | T5CON | 7:0 | CKPS[1:0] | SYNC | RD16 | ON | ||||
| 0x0FC4 | T5GCON | 7:0 | GE | GPOL | GTM | GSPM | GGO/DONE | GVAL | ||
| 0x0FC5 | TMR5GATE | 7:0 | GSS[3:0] | |||||||
| 0x0FC6 | TMR5CLK | 7:0 | CS[3:0] | |||||||
| 0x0FC7 | TMR3 | 7:0 | TMRxL[7:0] | |||||||
| 15:8 | TMRxH[7:0] | |||||||||
| 0x0FC9 | T3CON | 7:0 | CKPS[1:0] | SYNC | RD16 | ON | ||||
| 0x0FCA | T3GCON | 7:0 | GE | GPOL | GTM | GSPM | GGO/DONE | GVAL | ||
| 0x0FCB | TMR3GATE | 7:0 | GSS[3:0] | |||||||
| 0x0FCC | TMR3CLK | 7:0 | CS[3:0] | |||||||
| 0x0FCD | TMR1 | 7:0 | TMRxL[7:0] | |||||||
| 15:8 | TMRxH[7:0] | |||||||||
| 0x0FCF | T1CON | 7:0 | CKPS[1:0] | SYNC | RD16 | ON | ||||
| 0x0FD0 | T1GCON | 7:0 | GE | GPOL | GTM | GSPM | GGO/DONE | GVAL | ||
| 0x0FD1 | TMR1GATE | 7:0 | GSS[3:0] | |||||||
| 0x0FD2 | TMR1CLK | 7:0 | CS[3:0] | |||||||