12.3.4 Writing to the Data EEPROM Memory

To write an EEPROM data location, the address must first be written to the NVMADR register and the data written to the NVMDAT register. The sequence in NVM Unlock Sequence must be followed to initiate the write cycle.

The write will not begin if NVM Unlock sequence is not exactly followed for each byte. It is strongly recommended that interrupts be disabled during this code segment.

Additionally, the WREN bit must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit must be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, NVMCON1, NVMADR and NVMDAT cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. Both WR and WREN cannot be set with the same instruction.

After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. A single Data EEPROM word is written and the operation includes an implicit erase cycle for that word (it is not necessary to set FREE). CPU execution continues in parallel and at the completion of the write cycle, the WR bit is cleared in hardware and the NVM Interrupt Flag (NVMIF) bit is set. The user can either enable this interrupt or poll this bit. NVMIF must be cleared by software.

; Data Memory Address to write
        BCF     NVMCON1, NVMREG0    ; Setup Data EEPROM access
        BCF     NVMCON1, NVMREG1    ; Setup Data EEPROM access
        MOVF    EE_ADDRL, W         ;
        MOVWF   NVMADRL             ; Setup Address low byte
        MOVF    EE_ADDRH, W         ;
        MOVWF   NVMADRH             ; Setup Address high byte (if applicable)
; Data Memory Value to write
        MOVF    EE_DATA, W          ;
        MOVWF   NVMDAT              ;
; Enable writes
        BSF     NVMCON1, WREN       ;
; Disable interrupts
        BCF     INTCON, GIE         ;
; Required unlock sequence
        MOVLW   55h                 ;
        MOVWF   NVMCON2             ;
        MOVLW   AAh                 ;
        MOVWF   NVMCON2             ;
; Set WR bit to begin write
        BSF     NVMCON1, WR         ;
; Wait for write to complete
        BTFSC   NVMCON1, WR
        BRA     $-2
; Enable INT
        BSF     INTCON, GIE         ;
; Disable writes
        BCF     NVMCON1, WREN       ;