20.7.6 Timer1 Gate Event Interrupt

When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of GVAL occurs, the TMRxGIF flag bit in the PIR5 register will be set. If the TMRxGIE bit in the PIE5 register is set, then an interrupt will be recognized.

The TMRxGIF flag bit operates even when the Timer1 gate is not enabled (the GE bit is cleared).

For more information on selecting high or low priority status for the Timer1 gate event interrupt, refer to the “Interrupts” chapter.

Important: A pulse signal with minimum 100 ns width must be applied to TxGATE for proper operation. Any TxGATE pulse width that is shorter than 100 ns cannot be relied on to trigger an interrupt.