20.8 Timer1 Interrupt

The Timer1 register pair (TMRxH:TMRxL) increments to 0xFFFF and rolls over to 0x0000. When Timer1 rolls over, the Timer1 Interrupt Flag (TMR1IF) bit of the PIR4 register is set. To enable the interrupt-on-rollover, the following bits must be set:

• The TMRxON bit of the TxCON register
• The TMRxIE bits of the PIE4 register
• The PEIE/GIEL bit of the INTCON register
• The GIE/GIEH bit of the INTCON register

The interrupt is cleared by clearing the TMRxIF bit in the Interrupt Service Routine.

For more information on selecting high or low priority status for the Timer1 overflow interrupt, see the “Interrupts” chapter.