12.5.3 NVMADR

Data EEPROM Memory Address

Name:	NVMADR
Offset:	0xF7E


Bit	15	14	13	12	11	10	9	8
							NVMADRH[1:0]
Access							R/W	R/W
Reset							0	0


Bit	7	6	5	4	3	2	1	0
	NVMADRL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 9:8 – NVMADRH[1:0] EEPROM Most Significant Address bits

Note: This register is only implemented in devices with more than 256 bytes of data EEPROM.

Bits 7:0 – NVMADRL[7:0] EEPROM Least Significant Address bits

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