14.2 Configuration
The tables below show detailed programming sequences for PRBS, CW and additional CW mode. The R/W column indicates writing (W) or reading (R) a register or the Frame Buffer.
| Step | Action | Register | R/W | Value | Description |
|---|---|---|---|---|---|
| 1 | RESET | — | — | — | Reset AT86RF212B |
| 2 | Register access | 0x0E | W | 0x01 | Set IRQ mask register, enable IRQ_0 (PLL_LOCK) |
| 3 | Register access | 0x02 | W | 0x03 | Set radio transceiver state TRX_OFF |
| 4 | Register access | — | W | — | Set channel |
| 5 | Register access | — | W | — | Set TX output power. For CW mode, it is recommended GC_TX_OFFS be set to three(1). |
| 6 | Register access | 0x01 | R | 0x08 | Verify TRX_OFF state |
| 7 | Register access | 0x36 | W | 0x0F | — |
| 8 | Register access | 0x0C | W |
0x00 0x04 0x08 0x0C 0x1C 0x0A 0x0E |
Select PRBS mode with modulation scheme or CW mode with carrier position: PRBS mode, BPSK-20 PRBS mode, BPSK-40 PRBS mode, OQPSK-SIN-RC-100 PRBS mode, OQPSK-SIN-250 PRBS mode, OQPSK-RC-250 CW mode, CW at Fc – 0.1 MHz or CW at Fc + 0.1 MHz, see step 9 CW mode, CW at Fc – 0.25 MHz or CW at Fc + 0.25 MHz, see step 9 |
| 9 | Frame Buffer write access | — | W |
{PHR, PSDU} {0x01,0x00}{0x01, 0xFF}{0x01, 0x00}{0x01, 0xFF} |
PRBS mode: Write PHR value (0x01 … 0x7F) followed by PSDU data. PHR determines how many bytes of the PSDU data are repeated continuously. CW mode, CW at Fc – 0.1 MHz CW mode, CW at Fc + 0.1 MHz CW mode, CW at Fc – 0.25 MHz CW mode, CW at Fc + 0.25 MHz |
| 10 | Register access | 0x1C | W | 0x54 | — |
| 11 | Register access | 0x1C | W | 0x46 | — |
| 12 | Register access | 0x02 | W | 0x09 | Enable PLL_ON state |
| 13 | Interrupt event | 0x0F | R | 0x01 | Wait for IRQ_0 (PLL_LOCK) |
| 14 | Register access | 0x02 | W | 0x02 | Initiate transmission, enter BUSY_TX state |
| 15 | Measurement | — | — | — | Perform measurement |
| 16 | Register access | 0x1C | W | 0x00 | Disable Continuous Transmission Test Mode |
| 17 | Reset | — | — | — | Reset AT86RF212B |
| Step | Action | Register | R/W | Value | Description |
|---|---|---|---|---|---|
| 1 | Reset | — | — | — | Reset AT86RF212B rev. C |
| 2 | Register access | 0x0E | W | 0x01 | Set IRQ mask register, enable IRQ_0 (PLL_LOCK) |
| 3 | Register access | 0x02 | W | 0x03 | Set radio transceiver state TRX_OFF |
| 4 | Register access | — | W | — | Set channel |
| 5 | Register access | — | W | — | Set TX output power. For CW mode, set GC_TX_OFFS to three(1). |
| 6 | Register access | 0x01 | R | 0x08 | Verify TRX_OFF state |
| 7 | Register access | 0x36 | W | 0x0F | — |
| 8 | Register access | 0x1C | W | 0x54 | — |
| 9 | Register access | 0x1C | W | 0x42 | — |
| 10 | Register access | 0x34 | W | 0x00 | — |
| 11 | Register access | 0x3F | W | 0x08 | — |
| 12 | Register access | 0x02 | W | 0x09 | Enable PLL_ON state |
| 13 | Interrupt event | 0x0F | R | 0x01 | Wait for IRQ_0 (PLL_LOCK) |
| 14 | Register access | 0x02 | W | 0x02 | Initiate transmission, enter BUSY_TX state |
| 15 | Measurement | — | — | — | Perform measurement |
| 16 | Register access | 0x1C | W | 0x00 | Disable Continuous Transmission Test Mode |
| 17 | Reset | — | — | — | Reset AT86RF212B rev. C |
- Changing the output power during continuous transmission is not allowed.