2.3.3.1 UART RX Interface
(Ask a Question)The UART RX interface finite state machine receives the write request and write data from CORE_UART and provides the following data to the esmc_tx and esmc_rx subsystems:
- QL enable/disable: Determines whether ESMC IP operates in synchronous mode or non-synchronous mode.
- When ql_enabled is "1", design is in synchronous mode and processes the ESMC PDU's.
- When ql_enabled is "0", design is in non-synchronous mode and does not process ESMC PDU's.
- Local QL value: Local QL value of the EEC equipment is used after reset.
- Clear counter: Clear counter signal clears all the PDU counters.