2.3.3.2 UART TX Interface
(Ask a Question)The UART TX interface finite state machine receives the following design status and provides the status to CORE_UART upon receiving read request:
- QL enable/disable
- Current local QL value
- PRC info pdu count
- PRC event pdu count
- SSUA info pdu count
- SSUA event pdu count
- SSUB info pdu count
- SSUB event pdu count
- SEC info pdu count
- SEC event pdu count
- DNU info pdu count
- DNU event pdu count