3.3.7 Fractional-N PLL Register Overview

The following registers are used by the PLL. The RF front-end registers from the following table and the TX DSP registers from Table 3-2 must not be changed by application software. They are only used by firmware to control the start-up, power-down and calibration of the fractional-N PLL.

Table 3-1. RF Front-End Registers Used by Firmware
Register	Function
FESR.PLCK	PLL locked
FEEN1.PLSP1	PLL speedup
FEEN1.PLCAL	PLL calibration mode
FEEN1.PLEN	PLL enable
FEEN2.PLPEN	PLL post enable
FECR.PLCKG	PLL lock detect gate
FEVCT.FEVCT[3:0]	RF front-end VCO tuning register

Table 3-2. TX DSP Registers Used by Firmware
Register	Function
TDEN.SDEN	Sigma delta modulator enable for receive and transmit frequency synthesis
TDEN.SDPU	Sigma delta power-up

The RF front-end values, summarized in the following table are transferred from the factory-locked EEPROM to the RF front end by firmware before using the PLL.

Table 3-3. RF Front-End Registers for Factory-Locked Calibration
Register	Function
FEBT.RTN2[1:0]	Resistor tuning
FEBT.CTN2[1:0]	Capacitor tuning
FETN4.CTN4[3:0]	Capacitor tuning
FETN4.RTN4[3:0]	Resistor tuning
FEVCO.VCOB[3:0]	VCO bias 4-bit value⁽¹⁾
FEVCO.CPCC[3:0]	Charge pump current control⁽¹⁾

Note: For this register information, a calibration value from the factory-locked EEPROM and an application-specific value from the EEPROM settings are used. The register information must be copied to the RF front-end registers before using the PLL.

The TX DSP registers from Table 3-2 and RF front-end registers from Table 3-1 are changed due to application-specific settings coming from the EEPROM. The configuration tool must be used to calculate these EEPROM settings. The FFREQ settings can be modified there to compensate both the initial XTO and the XTAL frequency tolerances. The exact frequency steps of the PLL (f_XTO/2¹⁸ = 92.7 Hz in Low-Band frequency range and f_XTO/2¹⁷ = 185.43 Hz in High-Band when using a 24.3 MHz crystal) have to be considered.

Table 3-4. RF Front-End Registers Used for Application Settings
Register	Function
FEMS.M[3:0]	Main counter
FEMS.S[3:0]	Swallow counter
FECR.S4N3	Select 433MHz/315MHz band
FECR.LBNHB	Select Low-/High-Band
FEVCO.VCOB[3:0]	VCO bias ⁽¹⁾
FEVCO.CPCC[3:0]	Charge pump current control ⁽¹⁾

The following table shows the TX DSP settings used for frequency control (for more information, see TX DSP).

Table 3-5. TX DSP Registers Used for Application Settings
Register	Function
FSEN.PEEN	Preemphasis filtering enable
FSEN.GAEN	Gauss filtering enable
FSFCR.BTSEL	Gauss filter BT selection
GACDIV[12:0]	Gauss clock divider
FFREQ1[17:0]	Fractional frequency setting1
FFREQ2[17:0]	Fractional frequency setting2