32.9 Parallel Programming Characteristics

Table 32-12. Parallel programming characteristics, VCC = 5V ±10%.
SymbolParameterMin.Typ.Max.Units
VPPProgramming Enable Voltage11.5-12.5V
IPPProgramming Enable Current-250µA
tDVXHData and Control Valid before XTAL1 High67--ns
tXLXHXTAL1 Low to XTAL1 High300--ns
tXHXLXTAL1 Pulse Width High150--ns
tXLDXData and Control Hold after XTAL1 Low67--ns
tXLWLXTAL1 Low to WR Low0--ns
tXLPHXTAL1 Low to PAGEL high0--ns
tPLXHPAGEL low to XTAL1 high150--ns
tBVPHBS1 Valid before PAGEL High67--ns
tPHPLPAGEL Pulse Width High200--ns
tPLBXBS1 Hold after PAGEL Low67--ns
tWLBXBS2/1 Hold after WR Low67--ns
tPLWLPAGEL Low to WR Low67--ns
tBVWLBS2/1 Valid to WR Low67--ns
tWLWHWR Pulse Width Low150--ns
tWLRLWR Low to RDY/BSY Low0-1µs
tWLRHWR Low to RDY/BSY High(1)2-4.5ms
tWLRH_CEWR Low to RDY/BSY High for Chip Erase(2)7.5-12
tXLOLXTAL1 Low to OE Low0--ns
tBVDVBS1 Valid to DATA valid0-500
tOLDVOE Low to DATA Valid--500
tOHDZOE High to DATA Tri-stated--500
Note:
  1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.
  2. tWLRH_CE is valid for the Chip Erase command.
Figure 32-6. Parallel programming timing, including some general timing requirements.
Figure 32-7. Parallel programming timing, loading sequence with timing requirements
Note: The timing requirements shown in Figure 32-6 (that is, tDVXH, tXHXL, and tXLDX) also apply to loading operation.
Figure 32-8. Parallel programming timing, reading sequence (within the same page) with timing requirements
Note: The timing requirements shown in Figure 32-6 (that is, tDVXH, tXHXL, and tXLDX) also apply to loading operation.