The 2.2μF ceramic capacitor, which is connected to the VDD pin, must be located right at
the IC. The VDD pin is very noise sensitive and placement of the capacitor is critical. Use
wide traces to connect to the VDD and PGND pins.
The signal ground pin (SGND) must be connected directly to the ground planes. Do not route
the SGND pin to the PGND pad on the top layer.
Place the IC close to the point of load (POL).
Use wide traces to route the input and output power lines.
Signal and power grounds should be kept separate and connected at only one location.
DS20007156A
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