31.4 Signal Description

One signal can be mapped to any one of the several pins. For additional information, refer to the Pinout chapter.

To use the SERCOM’s I/O lines, the I/O pins must be configured using the IO Pin Controller (PORT). When the SERCOM is configured for SPI operation, the SERCOM controls the direction and value of the I/O pins as provided in the table below. The PORT Control bit, PINCFGn.DRVSTR, is still effective for the SERCOM output pins. The PORT Control bit, PINCFGn.PULLEN, is still effective for enabling/disabling a pull on the SERCOM input pins, but is limited to the enabling/disabling of a pull-down only (it is not possible to enable/disable a pull-up). If the receiver is disabled, the data input pin can be used for other purposes. In Host mode, the SPI Select line (SS) is hardware controlled when the Host SPI Select Enable bit in the Control B register (CTRLB.MSSEN) is '1'.

The combined configuration of PORT, the Data In Pinout and the Data Out Pinout bit groups in the Control A register (CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals in the table above.