34.5 Peripheral Dependencies
| Peripheral name | Base address | NVIC IRQ Index | AHB/APB Clocks | GCLK Peripheral Channel Index (GCLK.PCHCTRL) |
PAC Peripheral Identifier Index (PAC.WRCTRL) |
Events (EVSYS) | DMA Trigger Source Index (CHCTRLB.TRIGSRC) |
|
|---|---|---|---|---|---|---|---|---|
| Users (USERm) | Generators (CHANNELn.EVGEN) |
|||||||
| TC0 | 0x42003000 | 20: OVF | CLK_TC0_APB Disabled at reset |
30 | 76 Not protected at reset | 23: EVU | 53: OVF | 27: OVF |
| 20: MC0-1 | 54-55: MC0-1 | 28-29: MC0-1 | ||||||
| 20: ERR | ||||||||
| TC1 | 0x42003400 | 21: OVF | CLK_TC1_APB Disabled at reset |
30 | 77 Not protected at reset | 24: EVU | 56: OVF | 30: OVF |
| 21: MC0-1 | 57-58: MC0-1 | 31-32: MC0-1 | ||||||
| 21: ERR | ||||||||
| TC2 | 0x42003800 | 22: OVF | CLK_TC2_APB Disabled at reset |
31 | 78 Not protected at reset | 25: EVU | 59: OVF | 33: OVF |
| 22: MC0-1 | 60-61: MC0-1 | 34-35: MC0-1 | ||||||
| 22: ERR | ||||||||
| TC3 | 0x42003C00 | 23: OVF | CLK_TC3_APB Disabled at reset |
31 | 79 Not protected at reset | 26: EVU | 62: OVF | 36: OVF |
| 23: MC0-1 | 63-64: MC0-1 | 37-38: MC0-1 | ||||||
| 23: ERR | ||||||||
| TC4 | 0x42004000 | 24: OVF | CLK_TC4_APB Disabled at reset |
32 | 80 Not protected at reset | 27: EVU | 65: OVF | 39: OVF |
| 24: MC0-1 | 66-67: MC0-1 | 40-41: MC0-1 | ||||||
| 24: ERR | ||||||||
| TC5 | 0x43000800 | 20: OVF | CLK_TC5_APB Disabled at reset |
33 | 98 Not protected at reset | 45: EVU | 87: OVF | 53: OVF |
| 20: MC0-1 | 88-89: MC0-1 | 54-55: MC0-1 | ||||||
| 20: ERR | ||||||||
| TC6 | 0x43000C00 | 21: OVF | CLK_TC6_APB Disabled at reset |
34 | 99 Not protected at reset | 46: EVU | 90: OVF | 56: OVF |
| 21: MC0-1 | 91-92: MC0-1 | 57-58: MC0-1 | ||||||
| 21: ERR | ||||||||
| TC7 | 0x43001000 | 22: OVF | CLK_TC7_APB Disabled at reset |
35 | 100 Not protected at reset | 47: EVU | 93: OVF | 59: OVF |
| 22: MC0-1 | 94-95: MC0-1 | 60-61: MC0-1 | ||||||
| 22: ERR | ||||||||
Note: Several TC instances share the same
peripheral clock channel.