30.6.2.1 Initialization
The SERCOM bus clock (CLK_SERCOMx_APB) is required to access the SERCOM registers. This clock must be enabled as given in the MCLK - Main Clock Controller.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must be configured and enabled in the GCLK - Generic Clock Controller before using the SERCOMx_CORE.
The following registers are enable-protected, meaning they can only be written when the USART is disabled (CTRL.ENABLE = 0):
- The Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits.
- The Control B register (CTRLB), except the Receiver Enable (RXEN) and Transmitter Enable (TXEN) bits.
- The Baud register (BAUD)
When the USART is enabled or is being enabled (CTRLA.ENABLE = 1), any writing attempt to these registers will be discarded. If the peripheral is being disabled, writing to these registers will be executed after disabling is completed. Enable-protection is denoted by the "Enable-Protection" property in the register description.
Before the USART is enabled, it must be configured by these steps:
- Select either external (0x0) or internal clock (0x1) by writing the Operating mode value in the CTRLA register (CTRLA.MODE).
- Select either asynchronous (0) or synchronous (1) communication mode by writing the Communication Mode bit in the CTRLA register (CTRLA.CMODE).
- Select pin for receive data by writing the Receive Data Pinout value in the CTRLA register (CTRLA.RXPO).
- Select pads for the transmitter and external clock by writing the Transmit Data Pinout bit in the CTRLA register (CTRLA.TXPO).
- Configure the Character Size field in the CTRLB register (CTRLB.CHSIZE) for character size.
- Set the Data Order bit in the CTRLA register (CTRLA.DORD) to determine MSB-first or LSB-first data transmission.
- To use parity mode:
- Enable parity mode by writing 0x1 to the Frame Format field in the CTRLA register (CTRLA.FORM).
- Configure the Parity Mode bit in the CTRLB register (CTRLB.PMODE) for even or odd parity.
- Configure the number of stop bits in the Stop Bit Mode bit in the CTRLB register (CTRLB.SBMODE).
- When using an internal clock, write the Baud register (BAUD) to generate the desired baud rate.
- Enable the transmitter and receiver by writing '1' to the Receiver Enable and Transmitter Enable bits in the CTRLB register (CTRLB.RXEN and CTRLB.TXEN).