43.6.5 ICM Interrupt Disable Register

Name: IDR
Offset: 0x14
Reset: 0x00000000
Property: Write-Only

Bit 3130292827262524 
        URAD 
Access W 
Reset 0 
Bit 2322212019181716 
 RSU[3:0]REC[3:0] 
Access WWWWWWWW 
Reset 00000000 
Bit 15141312111098 
 RWC[3:0]RBE[3:0] 
Access WWWWWWWW 
Reset 00000000 
Bit 76543210 
 RDM[3:0]RHC[3:0] 
Access WWWWWWWW 
Reset 00000000 

Bit 24 – URAD Undefined Register Access Detection Interrupt Disable

ValueDescription
0 No effect.
1 Undefined Register Access Detection interrupt is disabled.

Bits 23:20 – RSU[3:0] Region Status Updated Interrupt Disable

ValueDescription
0 No effect.
1 When RSU[i] is written to '1', the region i Status Updated interrupt is disabled.

Bits 19:16 – REC[3:0] Region End bit Condition detected Interrupt Disable

ValueDescription
0 No effect.
1 When REC[i] is written to '1', the region i End bit Condition interrupt is disabled.

Bits 15:12 – RWC[3:0] Region Wrap Condition Detected Interrupt Disable

ValueDescription
0 No effect.
1 When RWC[i] is written to '1', the Region i Wrap Condition interrupt is disabled.

Bits 11:8 – RBE[3:0] Region Bus Error Interrupt Disable

ValueDescription
0 No effect.
1 When RBE[i] is written to '1', the Region i Bus Error interrupt is disabled.

Bits 7:4 – RDM[3:0] Region Digest Mismatch Interrupt Disable

ValueDescription
0 No effect.
1 When RDM[i] is written to '1', the Region i Digest Mismatch interrupt is disabled.

Bits 3:0 – RHC[3:0] Region Hash Completed Interrupt Disable

ValueDescription
0 No effect.
1 When RHC[i] is written to '1', the Region i Hash Completed interrupt is disabled.