36.7 Register Summary

Refer to the Registers Description section for more details on register properties and access permissions.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	CTRL	7:0		RUNSTDBY					ENABLE	SWRST
0x01 ... 0x03	Reserved
0x04	SEQCTRL0	7:0					SEQSEL[3:0]
0x05	SEQCTRL1	7:0					SEQSEL[3:0]
0x06 ... 0x07	Reserved
0x08	LUTCTRL0	31:24	TRUTH[7:0]
		23:16		LUTEO	LUTEI	INVEI	INSEL2[3:0]
		15:8	INSEL1[3:0]				INSEL0[3:0]
		7:0	EDGESEL		FILTSEL[1:0]				ENABLE
0x0C	LUTCTRL1	31:24	TRUTH[7:0]
		23:16		LUTEO	LUTEI	INVEI	INSEL2[3:0]
		15:8	INSEL1[3:0]				INSEL0[3:0]
		7:0	EDGESEL		FILTSEL[1:0]				ENABLE
0x10	LUTCTRL2	31:24	TRUTH[7:0]
		23:16		LUTEO	LUTEI	INVEI	INSEL2[3:0]
		15:8	INSEL1[3:0]				INSEL0[3:0]
		7:0	EDGESEL		FILTSEL[1:0]				ENABLE
0x14	LUTCTRL3	31:24	TRUTH[7:0]
		23:16		LUTEO	LUTEI	INVEI	INSEL2[3:0]
		15:8	INSEL1[3:0]				INSEL0[3:0]
		7:0	EDGESEL		FILTSEL[1:0]				ENABLE

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.