4.1.2 Startup Sequence

After a reset, the LAN8650/1 indicates to the host that a reset has occurred by asserting the IRQ_N pin and setting the RESETC bit of the OA_STATUS0 register. The device is now ready to be configured by the host controller before it can be used to transmit and receive data. When the host accesses the LAN8650/1 via SPI, it will also see that the SYNC bit of the OA_CONFIG0 register and of the data footer are cleared.

Once the host reads the OA_STATUS0, and determines that the cause of the interrupt was a reset, it should configure the LAN8650/1. As part of this configuration, there are two bits that must be written: the SYNC bit of the OA_CONFIG0 register must be set to indicate that the device is configured and ready to transmit and the RESETC bit of the OA_STATUS0 must be cleared so that IRQ_N line will stop asserting.

Figure 4-1. LAN8650/1 Startup and Configuration Sequence

The latest recommended startup configuration can be found in the LAN8650/1 Configuration Application Note AN1760. Additional details for customizing use of the MAC can be found in the Initialization section.