4.5.5 Phase Adjuster

When keeping a clock synchronized to an external clock source, it is necessary to regularly adjust the phase of the local clock. For example, in systems using the PTP SYNC message, this is usually sent from the clock source a few times a second, to enable local clocks to maintain alignment. When this message is received, early in clock acquisition, adjustments on the order of seconds may be needed. Very quickly, the systems will become better synchronized, but even then, it is not uncommon to need to make adjustments on the order of tens of nanoseconds. The time stamping clock of the internal MAC can be adjusted by single nanoseconds or single seconds. This requires many writes from the host to obtain and keep synchronization with the external source. The phase adjuster simplifies the programming on the controller, and additionally allows the change to be distributed over many clock cycles, smoothing out clock jitter and miminizing potential for inconsistent local timestamps.

The simplest way to use the phase adjuster is to write to the Phase Adjuster Control Register (PACTRL). This register enables selection of the clock delta, identifies whether it is in units of nanoseconds or of seconds, and if nanoseconds, whether the delta should be added or subtracted. When the phase adjuster is enabled by setting the Phase Adjust Active (ACT) bit, the clock time will be adjusted by one nanosecond (or one second) every clock cycle, for delta cycles. The ACT bit will be cleared at the end of the adjustment and the PADONE bit will be set in the Synchronization Event Status Register (SEVSTS). See the Synchronization Events section for more information on using this register.

If this value is only updated a few times a second, these adjustments could cause significant clock jitter, and large negative deltas could cause unexpected values in timestamps generated elsewhere in the system. To smooth out these changes and minimize jitter, the adjustments can be applied over many clock cycles, instead of at every clock edge. In this case, the Phase Adjuster Cycles Register (PACYC), should be written with the number of clock cycles between updates. This should be done before activating the adjuster via PACTRL.

As an example, suppose the clock needs to be sped up (decremented) by 25 nanoseconds. This could be done in 3 ways:
  1. Without using the phase adjuster, write to the MAC 25 times.
    • This will need to be done over SPI, and in a system with network traffic may not be done before the next SYNC packet arrives and a new clock adjustment is calculated.
  2. Using the phase adjuster, without using PACYC
    • Write PACTRL: DIF = 25, SEC = 0, DEC = 1 and ACT = 1 to decrement the clock 25ns, one ns per clock cycle (typically 40 ns).
    • This will take 25 timestamp clock cycles (typically 1 μs) to complete before the ACT bit is cleared. This entire period will exhibit additional clock jitter.
    • This requires one SPI control write.
  3. Use PACYC as well as PACTRL.
    • Write PACYC with the number of clock cycles between adjustments. Suppose this is 100.
    • Write PACTRL: DIF = 25, SEC = 0, DEC = 1 and ACT = 1 to begin to decrement the clock 25ns, one ns per 100 clock cycles.
    • This will take 2500 timestamp clock cycles (typically 100 μs) to complete before the ACT bit is cleared. 1% of the cycles will exhibit extra clock jitter.
    • This requires one SPI control write of 2 consecutive addresses.