11.2.20 TSU Timer Seconds High Register

Name:	MAC_TSH
Address:	0x070
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16

Access	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TCS[47:40]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TCS[39:32]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – TCS[47:32] Timer Count in Seconds

This register contains the upper 16 bits of the 48-bit timestamp unit seconds counter. It increments by 1 when the TSU nanoseconds counter counts to one second. It may also be incremented when the Timer Adjust Register is written.