1.3.1 Electrical Performance, HCSL

Table 1-3. Electrical Performance, HCSL
Parameter	Symbol	Min.	Typ.	Max.	Units
Supply
Voltage (Note 1)	V_DD	2.375	2.5	2.625	V
Voltage (Note 1)	V_DD	3.165	3.3	3.465	V
Current (Note 2)	I_DD	—	—	39	mA
Frequency
Nominal Frequency	f_N	13.5	—	170	MHz
Stability (Ordering Option, Note 3)	—	±25, ±50, ±100			ppm
Outputs
Output High, 2.5V	V_OH	580	—	850	mV
Output High, 3.3V	V_OH	600	—	850	mV
Output Low	V_OH	–150	—	150	mV
Output Logic Swing, 2.5V	V_OPP	0.60	—	—	V
Output Logic Swing, 3.3V	V_OPP	0.65		—	V
Output Rise and Fall Time (Note 3)	t_R/t_F	—	—	500	ps
Load	—	50Ω to ground			—
Duty Cycle (Note 4)	—	45	—	55	%
Jitter 100.000MHz (Note 5), 12kHz–20MHz	фJ	—	—	300	fs
Jitter 100.000MHz (Note 6),	фJ	PCIe Gen 1 – Gen 7 Compliant			—
Enable/Disable
Outputs Enabled (Note 8)	V_IH	0.7 × V_DD	—	—	V
Outputs Disabled	V_IL	—	—	0.3 × V_DD	V
Disable Time	t_D	—	—	200	ns
Enable/Disable Leakage Current	I_E/D	—	—	±200	uA
Start-Up Time	t_SU	—	—	10	ms
Operating Temperature (Ordering Option)	T_OP	–10/70 or –40/85			°C
Notes: The VC-709 power supply pin should be filtered, e.g., a 10uf, 0.1uf and 0.01uf capacitor. Figure 1-1 defines the test circuit and Figure 1-2 defines these parameters. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow. Duty Cycle is defined as the On Time/Period. Measured using an Agilent E5052. Measured using a LeCroy Wavemaster 8600A, 90K samples. Measured using a Wavecrest SIA3300C, 90K samples. Outputs will be Enabled if the Enable/Disable pad is left open.

Figure 1-1. HCSL Test Circuit

Figure 1-2. HCSL Output Parameters