1.3.2 Electrical Performance, LVDS

Table 1-4. Electrical Performance, LVDS
Parameter	Symbol	Min.	Typ.	Max.	Units
Supply
Voltage (Note 1)	V_DD	2.375	2.5	2.625	V
Voltage (Note 1)	V_DD	3.135	3.3	3.465	V
2.5V Current (Note 2)	I_DD	—	—	14	mA
3.3V Current (Note 2)	I_DD	—	—	17	mA
Frequency
Nominal Frequency	f_N	13.5	—	220.0	MHz
Stability (Ordering Option, Note 2)	—	±20, ±25, ±50, ±100			ppm
Outputs
Output Logic High (Note 2)	V_OH	—	1.43	1.6	V
Output Logic Low (Note 2)	V_OL	0.9	1.10	—	V
Output Amplitude	—	250	350	450	mV
Differential Output Error	—	—	—	50	mV
Output Leakage Current, Outputs Disabled	—	—	—	10	uA
Output Rise and Fall Time (Note 3)	t_R/t_F	—	—	400	ps
Load	—	100Ω differential
Duty Cycle (Note 4)	—	45	—	55	%
Jitter, 156.250MHz (12kHz – 50MHz, Note 5)	фJ	—	—	200	fs
Jitter, 156.250MHz (12kHz – 20MHz, Note 5)		—	—	150	fs
Jitter, 156.250MHz (10kHz – 1MHz, Note 5)		—	—	100	fs
Period Jitter, 156.250MHz (RMS, Note 6)	фJ	—	1.1	2.2	ps
Period Jitter, 156.250MHz (P/P, Note 6)		—	10.5	21.0	ps
Cycle-Cycle Jitter (RMS, Note 6)		—	1.9	3.8	ps
Cycle-Cycle Jitter (P/P, Note 6)		—	17.7	35.4	ps
Random Jitter (Note 7)		—	2.2	4.4	ps
Deterministic Jitter (Note 7)		—	0	—	ps
Enable/Disable
Outputs Enabled (Note 8)	V_IH	0.7 × V_DD	—	—	V
Output Disabled	V_IL	—	—	0.3 × V_DD	V
Disable Time	t_D	—	—	200	ns
Enable/Disable Leakage Current	I_E/D	—	—	±200	uA
Start-Up Time	t_SU	—	—	10	ms
Operating Temperature (Order Option)	T_OP	–10/70 or –40/85			°C
Notes: The VC-709 power supply pin should be filtered, e.g., a 10uf, 0.1uf and 0.01uf capacitor. Figure 1-4 defines these parameters and Figure 1-3 defines the test circuit. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow. Duty Cycle is defined as the On/Time Period. Measured using an Agilent E5052. Measured using a LeCroy Wavemaster 8600A, 90K samples. Measured using a Wavecrest SIA3300C, 90K samples. Outputs will be Enabled if Enable/Disable is left open.

Figure 1-3. LVDS Test Circuit

Figure 1-4. LVDS and LVPECL Output Parameters