4.5 UCSRD – USART Control and Status Register D
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
| Name: | UCSRD |
| Offset: | 0xC3 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXSIE | SFDE | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 7 – RXSIE USART RX Start Interrupt Enable
Writing this bit to one enables the interrupt on the RXS flag. In sleep modes this bit enables start frame detector that can wake up the MCU when a start condition is detected on the RxD line. The USART RX Start Interrupt is generated only if the RXSIE bit, the Global Interrupt Enable flag, and RXS are set.
Bit 5 – SFDE Start Frame Detection Enable
Writing this bit to one enables the USART Start Frame Detection mode. The start frame detector is able to wake up the MCU from sleep mode when a start condition, i.e. a high (IDLE) to low (START) transition, is detected on the RxD line.
| SFDE | RXSIE | RXSIE (RX complete interrupt enable) | Description |
|---|---|---|---|
| 0 | x | x | Start frame detection disabled |
| 1 | 0 | 0 | Reserved |
| 1 | 0 | 1 | Start frame detector enabled. The RXC flag will wake up the MCU from all sleep mode. |
| 1 | 1 | 0 | Start of frame detector enabled. The RXS flag will wake up the MCU from all sleep mode. |