16.5.2 Channel n Generator Selection
Each event channel can be connected to a single event generator.
Refer to the Peripheral Overview section for the available Event System channels.
| Name: | CHANNELn |
| Offset: | 0x10 + n*0x01 [n=0..3] |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHANNEL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – CHANNEL[7:0] Channel Generator Selection
Note: Not all generators can be connected to all channels. Refer
to the table below for further details.
Note:
- Not all peripheral instances are available for all pin counts. Refer to the Peripherals and Architecture chapter for details.
- Event from PORT pin will be zero if input driver is disabled.
- The operational mode of the timer decides when the CAPT flag is raised. Refer to the TCB section for details.
| GENERATOR | Async/Sync | Description | Channel Availability | ||
|---|---|---|---|---|---|
| Value | Name | ||||
| Peripheral(1) | Output | ||||
| 0x01 | UPDI | SYNCH | Async | Rising edge of SYNCH character detection | All channels |
| 0x06 | RTC | OVF | Async | Counter overflow | All channels |
| 0x07 | CMP | Compare match | |||
| 0x08 | EVGEN0 | Selectable prescaled RTC event | |||
| 0x09 | EVGEN1 | ||||
| 0x10 | CCL | LUT0 | Async | LUT output level | All channels |
| 0x11 | LUT1 | ||||
| 0x12 | LUT2 | ||||
| 0x13 | LUT3 | ||||
| 0x20 | AC0 | OUT | Async | Comparator output level | All channels |
| 0x24 | ADC0 | RES | Sync | Result ready | All channels |
| 0x25 | SAMP | Sample ready | |||
| 0x26 | WCMP | Window comparison match | |||
| 0x40 | PORTA | EVGEN0 | Async | Pin level(2) | All channels |
| 0x41 | EVGEN1 | ||||
| 0x44 | PORTC | EVGEN0 | Async | Pin level(2) | All channels |
| 0x45 | EVGEN1 | ||||
| 0x46 | PORTD | EVGEN0 | Async | Pin level(2) | All channels |
| 0x47 | EVGEN1 | ||||
| 0x4A | PORTF | EVGEN0 | Async | Pin level(2) | All channels |
| 0x4B | EVGEN1 | ||||
| 0x60 | USART0 | XCK | Sync | Clock signal in SPI Host mode and synchronous USART Host mode | All channels |
| 0x68 | SPI0 | SCK | Sync | SPI Host clock signal | All channels |
| 0x80 | TCE0 | OVF | Sync | Overflow/Low-byte timer underflow | All channels |
| 0x84 | CMP0 | Sync | Compare channel 0 match/Low-byte timer compare channel 0 match | ||
| 0x85 | CMP1 | Compare channel 1 match/Low-byte timer compare channel 1 match | |||
| 0x86 | CMP2 | Compare channel 2 match/Low-byte timer compare channel 2 match | |||
| 0xA0 | TCB0 | CAPT | Sync | CAPT Interrupt flag set(3) | All channels |
| 0xA1 | OVF | Counter overflow | |||
| 0xA2 | TCB1 | CAPT | Sync | CAPT Interrupt flag set(3) | All channels |
| 0xA3 | OVF | Counter overflow | |||
