7.6.7.3 PDMC Configuration Register

This register can only be written if the WPEN bit is cleared in PDMC_WPMR.

Name: PDMC_CFGR
Offset: 0x08
Reset: 0x00500044
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
  PDMSEL3 PDMSEL2 PDMSEL1 PDMSEL0 
Access R/WR/WR/WR/W 
Reset 1100 
Bit 15141312111098 
    PACK DATAL[2:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
  BSSEL3 BSSEL2 BSSEL1 BSSEL0 
Access R/WR/WR/WR/W 
Reset 1010 

Bits 16, 18, 20, 22 – PDMSELx PDM Microphone Source Selection

ValueNameDescription
0 DS0 PDMSELx corresponds to PMDC_DS0.
1 DS1 PDMSELx corresponds to PMDC_DS1.

Bit 12 – PACK Packed Data

ValueDescription
0 Data are not packed.
1 Data are packed (if the DATAL configuration allows packing).

Bits 10:8 – DATAL[2:0] Data Length

Defines the length of the data defined in PDMC_RHR.
ValueNameDescription
0 24_BITS Data are defined on 24 bits.
1 32_BITS Data are defined on 32 bits.
2 20_BITS Data are defined on 20 bits.
3 16_BITS Data are defined on 16 bits.
4 8_BITS Data are defined on 8 bits.

Bits 0, 2, 4, 6 – BSSELx Bitstream Source Selection

ValueDescription
0 The selected PDMC_DSx source is sampled on the positive edge of PDMC_CLK.
1 The selected PDMC_DSx source is sampled on the negative edge of PDMC_CLK.