7.6.7.11 PDMC Fault Injection Register

This register can only be written if FIRDIS is cleared.

Name: PDMC_FIR
Offset: 0x38
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 FIKEY[23:16] 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 FIKEY[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 FIKEY[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 FIRDIS SFEN F3F2F1F0 
Access R/WWWWWW 
Reset 000000 

Bits 31:8 – FIKEY[23:0] Fault Injection Key

ValueNameDescription
0x504649 PASSWD Writing any other value in this field aborts the write operation. Always reads as 0.

Bit 7 – FIRDIS Fault Injection Register Disable

ValueNameDescription
0 NO_EFFECT No effect.
1 ACTIVE Disables the fault injection until the next hardware reset. The command is valid only if PDMC_WPSR.NCE=0 and the other bits are cleared (F0=F1=F2=F3=SFEN=0).

Bit 5 – SFEN Single Fault Enable

Always write to '1' for fault injection

Bit 3 – F3 Single Fault for Write Protection Mode Register (PDMC_WPMR)

ValueDescription
0 No effect.
1 Creates a single fault in the error detection circuitry of PDMC_WPMR (the configuration is not modified) which triggers PDMC_WPSR.NCE to '3'.

Bit 2 – F2 Single Fault for Interrupt Mask Register (PDMC_IMR)

ValueDescription
0 No effect.
1 Creates a single fault in the error detection circuitry of PDMC_IMR (the configuration is not modified) which triggers PDMC_WPSR.NCE to '3'.

Bit 1 – F1 Single Fault for Configuration Register (PDMC_CFGR)

ValueDescription
0 No effect.
1 Creates a single fault in the error detection circuitry of PDMC_CFGR (the configuration is not modified) which triggers PDMC_WPSR.NCE to '3'.

Bit 0 – F0 Single Fault for Mode Register (PDMC_MR)

ValueDescription
0 No effect.
1 Creates a single fault in the error detection circuitry of PDMC_MR (the configuration is not modified) which triggers PDMC_WPSR.NCE to '3'.