| General | Added content related to the SAMA7D65(T)-V/7EW(-SLx)
device |
| Debug and Test | JTAG Debug Port
(JTAG-DP), Serial Wire Debug Port
(SW-DP): updated VERSION and DESIGNER descriptions |
| Boot Strategies | Updated Description, Secure Boot Configuration Packet |
| Static Memory Controller (SMC) | HSMC_SETUPx, HSMC_PULSEx: corrected register
access to “Read/Write” |
| DDR/LPDDR Physical Interface (DDR3PHY) | Updated DDR3PHY_MRx register names |
| Real-Time Clock (RTC) |
Updated UTC Mode
RTC_MR:
updated the UTC and HRMODE descriptions
RTC_TIMALR (DEFAULT_MODE):
updated the AMPM bit description
|
| Advanced Encryption Standard (AES) |
Updated Start Modes, Encrypted Tweak Generation,
Data Processing
XEX-based Tweaked-codebook Mode (XTS):
updated auto-padding information
|
| Flexible Serial Communication Controller (FLEXCOM) |
Modified content regarding multiple data reading in SPI Multiple Data Access, FLEX_SPI_RDR (FIFO_MULTI_DATA_8), FLEX_SPI_RDR (FIFO_MULTI_DATA_16)
FLEX_SPI_RDR (FIFO_MULTI_DATA_8),
FLEX_SPI_RDR (FIFO_MULTI_DATA_16),
FLEX_SPI_TDR (FIFO_MULTI_DATA):
“FIFO” removed from register name (but kept in register acronym)
|
| Secure Digital MultiMedia Card Controller (SDMMC) |
SDMMC_CALCR:
updated CLKDIV description
SDMMC SDMA System Address/Argument 2 Register split into SDMMC_SSAR (DEFAULT_MODE) and SDMMC_SSAR (CMD23)
|
| Electrical Characteristics |
Table 11-4: updated VDDCPU conditions
Table 11-6: updated fCPU_CLK conditions
Table 11-76: updated Use Case 6 values
Reworked Flexible Serial Communication Controller
(FLEXCOM) - USART
|
