34.12.2 Control B
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLB |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIFOCLR[1:0] | ACKACT | CMD[1:0] | |||||||
| Access | RW | RW | RW | W | W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| AMODE[1:0] | AACKEN | GCMD | SMEN | ||||||
| Access | RW | RW | RW | RW | RW | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bits 23:22 – FIFOCLR[1:0] FIFO Clear
When these bits are set, the corresponding FIFO will be cleared. The bits will automatically clear when SYNCBUSY.SYSOP = 0.
These bits are not enable-protected.
| FIFOCLR[1:0] | Name | Description |
|---|---|---|
| 0x0 | NONE | No action |
| 0x1 | TXFIFO | Clear TX FIFO |
| 0x2 | RXFIFO | Clear RX FIFO |
| 0x3 | BOTH | Clear both TX/RX FIFO |
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | No action |
| 0x1 | TXFIFO | Clear TX FIFO |
| 0x2 | RXFIFO | Clear RX FIFO |
| 0x3 | BOTH | Clear both TX and RF FIFOs |
Bit 18 – ACKACT Acknowledge Action
This bit defines the client's acknowledge behavior after an address or data byte is received from the host. The acknowledge action is executed when a command is written to the CMD bits. If smart mode is enabled (CTRLB.SMEN=1), the acknowledge action is performed when the DATA register is read.
ACKACT shall not be updated more than once between each peripheral interrupts request.
This bit is not enable-protected. This bit is not write-synchronized.
CTRLB.ACKACT shall not be updated more than once between each peripheral interrupt request.
| Value | Description |
|---|---|
| 0 | Send ACK |
| 1 | Send NACK |
Bits 17:16 – CMD[1:0] Command
This bit field triggers the client operation as shown below. The CMD bits are strobe bits, and always read as zero. The operation is dependent on the client interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH, in addition to STATUS.DIR.
All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a command is given.
This bit is not enable-protected. This bit is not write-synchronized.
| CMD[1:0] | STATUS.DIR Value | Action |
|---|---|---|
| 0x0 | X | (No action) |
| 0x1 | X | (Reserved) |
| 0x2 | Used to complete a transaction in response to a data interrupt (DRDY) | |
| 0 (Host write) | Execute acknowledge action succeeded by waiting for any start (S/Sr) condition | |
| 1 (Host read) | Wait for any start (S/Sr) condition | |
| 0x3 | Used in response to an address interrupt (AMATCH) | |
| 0 (Host write) | Execute acknowledge action succeeded by reception of next byte | |
| 1 (Host read) | Execute acknowledge action succeeded by client data interrupt | |
| Used in response to a data interrupt (DRDY) | ||
| 0 (Host write) | Execute acknowledge action succeeded by reception of next byte | |
| 1 (Host read) | Execute a byte read operation followed by ACK/NACK reception | |
Bits 15:14 – AMODE[1:0] Address Mode
These bits set the addressing mode.
These bits are not write-synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | MASK | The slave responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK |
| 0x1 | 2ADDRS | The slave responds to the two unique addresses in ADDR and ADDRMASK |
| 0x2 | RANGE | The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit |
Bit 10 – AACKEN Automatic Address Acknowledge
This bit enables the address to be automatically acknowledged if there is an address match.
This bit is not write-synchronized.
| Value | Description |
|---|---|
| 0 | Automatic acknowledge is disabled. |
| 1 | Automatic acknowledge is enabled. |
Bit 9 – GCMD PMBus Group Command
This bit enables PMBus group command support. When enabled, the Stop Received interrupt flag (INTFLAG.PREC) will be set when a STOP condition is detected if the client has been addressed since the last STOP condition on the bus.
This bit is not write-synchronized.
| Value | Description |
|---|---|
| 0 | Group command is disabled. |
| 1 | Group command is enabled. |
Bit 8 – SMEN Smart Mode Enable
When smart mode is enabled, data is acknowledged automatically when DATA.DATA is read.
This bit is not write-synchronized.
| Value | Description |
|---|---|
| 0 | Smart mode is disabled. |
| 1 | Smart mode is enabled. |