34.12.13 FIFO CPU Pointers

Table 34-80. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	FIFOPTR
Offset:	0x36
Reset:	0x0000
Property:	RW


Bit	15	14	13	12	11	10	9	8
					CPURDPTR[3:0]
Access					RW	RW	RW	RW
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
					CPUWRPTR[3:0]
Access					RW	RW	RW	RW
Reset					0	0	0	0

Bits 11:8 – CPURDPTR[3:0] CPU FIFO Read Pointer

These bits return the CPURDPTR pointer value. These bits can be written only if the SERCOM is halted during debugging. Reading DATA register, will return RXFIFO[CPURDPTR] location value.

Bits 3:0 – CPUWRPTR[3:0] CPU FIFO Write Pointer

These bits return the CPUWRPTR pointer value. These bits can be written only if the SERCOM is halted during debugging. When writing to DATA register, the DATA will be written to TXFIFO[CPUWRPTR] location.