34.9.1 Control A

Table 34-21. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—


Bit	31	30	29	28	27	26	25	24
		DORD	CPOL	CMODE	FORM[3:0]
Access		RW	RW	RW	RW	RW	RW	RW
Reset		0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	SAMPA[1:0]		RXPO[1:0]				TXPO[1:0]
Access	RW	RW	RW	RW			RW	RW
Reset	0	0	0	0			0	0


Bit	15	14	13	12	11	10	9	8
	SAMPR[2:0]					RXINV	TXINV	IBON
Access	RW	RW	RW			RW	RW	RW
Reset	0	0	0			0	0	0


Bit	7	6	5	4	3	2	1	0
	RUNSTDBY			MODE[2:0]			ENABLE	SWRST
Access	RW			RW	RW	RW	RW	RW
Reset	0			0	0	0	0	0

Bit 30 – DORD Data Order

This bit selects the data order when a character is shifted out from the Data register.

This bit is not synchronized.

Value	Name	Description
0x0	MSB	MSB is transmitted first.
0x1	LSB	LSB is transmitted first.

Bit 29 – CPOL Clock Polarity

This bit selects the relationship between data output change and data input sampling in synchronous mode.

This bit is not synchronized.


CPOL	TxD Change	RxD Sample
0x0	Rising XCK edge	Falling XCK edge
0x1	Falling XCK edge	Rising XCK edge

Bit 28 – CMODE Communication Mode

This bit selects asynchronous or synchronous communication.

This bit is not synchronized.

Value	Name	Description
0x0	ASYNC	Asynchronous communication.
0x1	SYNC	Synchronous communication.

Bits 27:24 – FORM[3:0] Frame Format

These bits define the frame format.

These bits are not synchronized.


FORM[3:0]	Description
0x0	USART frame
0x1	USART frame with parity
0x2	LIN Hosst - Break and sync generation. See LIN Command (CTRLB.LINCMD).
0x3	Reserved
0x4	Auto-baud (LIN Client) - break detection and auto-baud.
0x5	Auto-baud - break detection and auto-baud with parity
0x6 - 0xF	Reserved

Value	Name	Description
0x0	USART	USART frame
0x1	USARTP	USART frame with parity
0x2	LINBRKGEN	LIN Master Break and Synck generation
0x4	LINBRKDET	LIN Slave break detection and auto-baud
0x5	BRKDET	Break detection and auto-baud with parity

Bits 23:22 – SAMPA[1:0] Sample Adjustment

These bits define the sample adjustment.

These bits are not synchronized.


SAMPA[1:0]	16x Over-sampling (CTRLA.SAMPR=0 or 1)	8x Over-sampling (CTRLA.SAMPR=2 or 3)
0x0	7-8-9 (Recommended)	3-4-5 (Recommended)
0x1	9-10-11	4-5-6
0x2	11-12-13	5-6-7
0x3	13-14-15	6-7-8

Bits 21:20 – RXPO[1:0] Receive Data Pinout

These bits define the receive data (RxD) pin configuration.

These bits are not synchronized.


RXPO[1:0]	Name	Description
0x0	PAD[0]	SERCOM PAD[0] is used for data reception
0x1	PAD[1]	SERCOM PAD[1] is used for data reception
0x2	PAD[2]	SERCOM PAD[2] is used for data reception
0x3	PAD[3]	SERCOM PAD[3] is used for data reception

Value	Name	Description
0x0	PAD0	SERCOM PAD0 is used for data reception
0x1	PAD1	SERCOM PAD1 is used for data reception
0x2	PAD2	SERCOM PAD2 is used for data reception
0x3	PAD3	SERCOM PAD3 is used for data reception

Bits 17:16 – TXPO[1:0] Transmit Data Pinout

These bits define the transmit data (TxD) and XCK pin configurations.

This bit is not synchronized.


TXPO	TxD Pin Location	XCK Pin Location (When Applicable)	RTS/TE	CTS
0x0	SERCOM PAD[0]	SERCOM PAD[1]	N/A	N/A
0x1	Reserved
0x2	SERCOM PAD[0]	N/A	SERCOM PAD[2]	SERCOM PAD[3]
0x3	SERCOM PAD[0]	SERCOM PAD[1]	SERCOM PAD[2]	N/A

Value	Name	Description
0x0	PAD0	PAD[0] = TxD; PAD[1] = XCK
0x2	PAD2	PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS
0x3	PAD3	PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE

Bits 15:13 – SAMPR[2:0] Sample

These bits select the sample rate.

These bits are not synchronized.


SAMPR[2:0]	Description
0x0	16x over-sampling using arithmetic baud rate generation.
0x1	16x over-sampling using fractional baud rate generation.
0x2	8x over-sampling using arithmetic baud rate generation.
0x3	8x over-sampling using fractional baud rate generation.
0x4	3x over-sampling using arithmetic baud rate generation.
0x5-0x7	Reserved

Value	Name	Description
0x0	ARITHM16X	16x oversampling using arithmetic baud rate generation
0x1	FRAC16X	16x oversampling using fractional baud rate generation
0x2	ARITHM8X	8x oversampling using arithmetic baud rate generation
0x3	FRAC8X	8x oversampling using fractional baud rate generation
0x4	ARITHM3X	3x oversampling using arithmetic baud rate generation

Bit 10 – RXINV Receive Data Invert

Value	Name	Description
0x0	DISABLE	RxD is not inverted
0x1	INV	RxD is inverted

Bit 9 – TXINV Transmit Data Invert

Value	Name	Description
0x0	DISABLE	TxD is not inverted
0x1	INV	TxD is inverted

Bit 8 – IBON Immediate Buffer Overflow Notification

This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.

Value	Description
0	STATUS.BUFOVF is asserted when it occurs in the data stream.
1	STATUS.BUFOVF is asserted immediately upon buffer overflow.

Bit 7 – RUNSTDBY Run during Standby

This bit defines the functionality in standby sleep mode.

This bit is not synchronized.


RUNSTDBY	External Clock	Internal Clock
0x0	External clock is disconnected when ongoing transfer is finished. All reception is dropped.	Generic clock is disabled when ongoing transfer is finished. The device will not wake up on either Receive Start or Transfer Complete interrupt unless the appropriate ONDEMAND bits are set in the clocking chain.
0x1	Wake on Receive Start or Receive Complete interrupt.	Generic clock is enabled in all sleep modes. Any interrupt can wake up the device.

Bits 4:2 – MODE[2:0] Operating Mode

These bits select the USART serial communication interface of the SERCOM.

These bits are not synchronized.

Value	Name	Description
0x0	EXTCLK	USART with external clock
0x1	INTCLK	Usart with internal clock

Bit 1 – ENABLE Enable

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete.

This bit is not enable-protected.

Value	Description
0	The peripheral is disabled or being disabled.
1	The peripheral is enabled or being enabled.

Bit 0 – SWRST Software Reset

Writing '0' to this bit has no effect.

Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.

Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in a bus error. Reading any register will return the reset value of the register.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.

This bit is not enable-protected.

Note:

When the CTRLA.SWRST is written, the user should poll the SYNCB.SWRST bit to know when the reset operation is complete.
During a SWRST, access to registers/bits without SWRST are disallowed until the SYNCBUSY.SWRST is cleared by the hardware.

Value	Description
0	There is no reset operation ongoing.
1	The reset operation is ongoing.

Name:	CTRLA
Offset:	0x00
Reset:	0x00000000
Property:	RW