34.9.3 Control C

Table 34-23. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CTRLC
Offset:	0x08
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	TXTRHOLD[1:0]		RXTRHOLD[1:0]		FIFOEN		DATA32B[1:0]
Access	RW	RW	RW	RW	RW		R/W	R/W
Reset	0	0	0	0	0		0	0


Bit	23	22	21	20	19	18	17	16
		MAXITER[2:0]					DSNACK	INACK
Access		RW	RW	RW			RW	RW
Reset		0	0	0			0	0


Bit	15	14	13	12	11	10	9	8
					HDRDLY[1:0]		BRKLEN[1:0]
Access					RW	RW	RW	RW
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
						GTIME[2:0]
Access						RW	RW	RW
Reset						0	0	0

Bits 31:30 – TXTRHOLD[1:0] Transmit FIFO Threshold

These bits define the threshold for generating the Data Register Empty interrupt and DMA TX trigger.


TXTRHOLD	Name	Description
0	DEFAULT	Interrupt and DMA triggers can be generated as long as the FIFO is not full.
1	HALF	Interrupt and DMA triggers are generated when half FIFO space is free.
2	EMPTY	Interrupt and DMA triggers are generated when the FIFO is empty.
3	-	Reserved

Value	Name	Description
0x0	DEFAULT	Interrupt and DMA triggers are generated as long as the FIFO is not full
0x1	HALF	Interrupt and DMA triggers are generated when half FIFO space is free
0x2	EMPTY	Interrupt and DMA triggers are generated when the FIFO is empty

Bits 29:28 – RXTRHOLD[1:0] Receive FIFO Threshold

These bits define the threshold for generating the RX Complete interrupt and DMA RX trigger.


RXTRHOLD	Name	Description
0	DEFAULT	Interrupt and DMA triggers can be generated when a DATA is present in the FIFO.
1	HALF	Interrupt and DMA triggers can be generated only when the FIFO is half-full.
2	FULL	Interrupt and DMA triggers can be generated only when the FIFO is full.
3	-	Reserved

Value	Name	Description
0x0	DEFAULT	Interrupt and DMA triggers are generated when DATA is present in the FIFO
0x1	HALF	Interrupt and DMA triggers are generated when FIFO is half-full
0x2	FULL	Interrupt and DMA triggers are generated when FIFO is full

Bit 27 – FIFOEN FIFO Enable

This bit enables the FIFO operation.

Value	Description
0	FIFO operation is disabled
1	FIFO operation is enabled

Bits 25:24 – DATA32B[1:0] Data 32 Bit

These bits configure 32-bit Extension for read and write transactions to the DATA register.

When disabled, access is according to CTRLB.CHSIZE.

Value	Description
0x0	DATA reads (for received data) and writes (for transmit data) according to CTRLB.CHSIZE.
0x1	DATA reads according to CTRLB.CHSIZE. DATA writes using 32-bit Extension.
0x2	DATA reads using 32-bit Extension. DATA writes according to CTRLB.CHSIZE.
0x3	DATA reads and writes using 32-bit Extension.

Bits 22:20 – MAXITER[2:0] Maximum Iterations

Bit 17 – DSNACK Disable Successive NACK

Bit 16 – INACK Inhibit Not Acknowledge

Bits 11:10 – HDRDLY[1:0] LIN Master Header Delay

These bits define the delay between break and sync transmission in addition to the delay between the sync and identifier (ID) fields when in LIN host mode (CTRLA.FORM=0x2).

This field is only valid when using the LIN header command (CTRLB.LINCMD=0x2).

Note: A correct setting for this bit field must be selected in order to follow the LIN specification.

Value	Name	Description
0x0	1BIT	Delay between break and sync transmission is 1-bit time
0x1	4BITS	Delay between break and sync transmission is 4-bit time
0x2	8BITS	Delay between break and sync transmission is 8-bit time
0x3	14BITS	Delay between break and sync transmission is 14-bit time

Bits 9:8 – BRKLEN[1:0] LIN Master Break Length

These bits define the length of the break field transmitted when in LIN host mode (CTRLA.FORM=0x2).

Note: A correct setting for this bit field must be selected in order to follow the LIN specification.

Value	Name	Description
0x0	13BITS	Break field transmission is 13 bit times
0x1	17BITS	Break field transmission is 17 bit times
0x2	21BITS	Break field transmission is 21 bit times
0x3	26BITS	Break field transmission is 26 bit times

Bits 2:0 – GTIME[2:0] Guard Time

These bits define the guard time when using RS485 mode (CTRLA.FORM=0x0 or CTRLA.FORM=0x1, and CTRLA.TXPO=0x3).

For RS485 mode, the guard time is programmable from 0-7 bit times and defines the time that the transmit enable pin (TE) remains high after the last stop bit is transmitted and there is no remaining data to be transmitted.