25.9.3 Event Control

Table 25-28. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	EVCTRL
Offset:	0x04
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
								PERDEO
Access								RW
Reset								0


Bit	23	22	21	20	19	18	17	16
								TAMPEVEI
Access								RW
Reset								0


Bit	15	14	13	12	11	10	9	8
	OVFEO	TAMPEREO			ALARMEO[3:0]
Access	RW	RW			RW	RW	RW	RW
Reset	0	0			0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PEREO[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bit 24 – PERDEO Periodic Interval Daily Event Output Enable

Value	Description
0	Periodic Daily event is disabled and will not be generated.
1	Periodic Daily event is enabled and will be generated. The event occurs at the last second of each day depending on the CTRLA.CLKREP bit: If CLKREP = 0, the event will occur at 23:59:59 If CLKREP = 1, the event will occur at 11:59:59, PM = 1

Bit 16 – TAMPEVEI Tamper Event Input Enable

Value	Description
0	Tamper event input is disabled, and incoming events will be ignored.
1	Tamper event input is enabled, and all incoming events will capture the CLOCK value.

Bit 15 – OVFEO Overflow Event Output Enable

Value	Description
0	Overflow event is disabled and will not be generated.
1	Overflow event is enabled and will be generated for every overflow.

Bit 14 – TAMPEREO Tamper Event Output Enable

Value	Description
0	Tamper event output is disabled, and will not be generated
1	Tamper event output is enabled, and will be generated for every tamper input.

Bits 11:8 – ALARMEO[3:0] Alarm x Event Output Enable

Bits 7:0 – PEREO[7:0] Periodic Interval x Event Output Enable