25.9.2 Control B

Table 25-27. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CTRLB
Offset:	0x02
Reset:	0x0000
Property:	RW


Bit	15	14	13	12	11	10	9	8
	SEPTO	ACTF[2:0]				DEBF[2:0]
Access	RW	RW	RW	RW		RW	RW	RW
Reset	0	0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
	DMAEN	RTCOUT	DEBASYNC	DEBMAJ	GP6EN	GP4EN	GP2EN	GP0EN
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bit 15 – SEPTO Separate Tamper Outputs

Bits 14:12 – ACTF[2:0] Active Layer Frequency

Value	Name	Description
0x0	DIV2	CLK_RTC_OUT = CLK_RTC/2
0x1	DIV4	CLK_RTC_OUT = CLK_RTC/4
0x2	DIV8	CLK_RTC_OUT = CLK_RTC/8
0x3	DIV16	CLK_RTC_OUT = CLK_RTC/16
0x4	DIV32	CLK_RTC_OUT = CLK_RTC/32
0x5	DIV64	CLK_RTC_OUT = CLK_RTC/64
0x6	DIV128	CLK_RTC_OUT = CLK_RTC/128
0x7	DIV256	CLK_RTC_OUT = CLK_RTC/256

Bits 10:8 – DEBF[2:0] Debounce Frequency

Value	Name	Description
0x0	DIV2	CLK_RTC_DEB = CLK_RTC/2
0x1	DIV4	CLK_RTC_DEB = CLK_RTC/4
0x2	DIV8	CLK_RTC_DEB = CLK_RTC/8
0x3	DIV16	CLK_RTC_DEB = CLK_RTC/16
0x4	DIV32	CLK_RTC_DEB = CLK_RTC/32
0x5	DIV64	CLK_RTC_DEB = CLK_RTC/64
0x6	DIV128	CLK_RTC_DEB = CLK_RTC/128
0x7	DIV256	CLK_RTC_DEB = CLK_RTC/256

Bit 7 – DMAEN DMA Enable

Bit 6 – RTCOUT RTC Output Enable

Bit 5 – DEBASYNC Debouncer Asynchronous Enable

Bit 4 – DEBMAJ Debouncer Majority Enable

Bit 3 – GP6EN General Purpose 6 Enable

Bit 2 – GP4EN General Purpose 4 Enable

Bit 1 – GP2EN General Purpose 2 Enable

Bit 0 – GP0EN General Purpose 0 Enable