25.9.7 Synchronization Busy Status

Table 25-32. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	SYNCBUSY
Offset:	0x10
Reset:	0x00000000
Property:	R


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	GP[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CLOCKSYNC	MASK[3:0]						ALARM[3]
Access	R	R	R	R	R			R
Reset	0	0	0	0	0			0


Bit	7	6	5	4	3	2	1	0
	ALARM[2:0]				CLOCK	FREQCORR	ENABLE	SWRST
Access	R	R	R		R	R	R	R
Reset	0	0	0		0	0	0	0

Bits 23:16 – GP[7:0] General Purpose x Register Busy

Bit 15 – CLOCKSYNC Clock Synchronization Enable Bit Busy

Value	Description
0	Write synchronization for CTRLA.CLOCKSYNC bit is complete.
1	Write synchronization for CTRLA.CLOCKSYNC bit is ongoing.

Bits 14:11 – MASK[3:0] MASK x Register Busy

Bits 8:5 – ALARM[3:0] ALARM x Register Busy

Bit 3 – CLOCK CLOCK Register Busy

Value	Description
0	Read/write synchronization for CLOCK register is complete.
1	Read/write synchronization for CLOCK register is ongoing.

Bit 2 – FREQCORR FREQCORR Register Busy

Value	Description
0	Write synchronization for FREQCORR register is complete.
1	Write synchronization for FREQCORR register is ongoing.

Bit 1 – ENABLE Enable Bit Busy

Value	Description
0	Write synchronization for CTRLA.ENABLE bit is complete.
1	Write synchronization for CTRLA.ENABLE bit is ongoing.

Bit 0 – SWRST Software Reset Bit Busy

Value	Description
0	Write synchronization for CTRLA.SWRST bit is complete.
1	Write synchronization for CTRLA.SWRST bit is ongoing.

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