25.9.5 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.

Table 25-30. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	INTENSET
Offset:	0x0A
Reset:	0x0000
Property:	RW


Bit	15	14	13	12	11	10	9	8
	OVF	TAMPER			ALARM[3:0]
Access	RW	RW			RW	RW	RW	RW
Reset	0	0			0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PER[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bit 15 – OVF Overflow Interrupt Enable

Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt.

Value	Description
0	The Overflow interrupt is disabled.
1	The Overflow interrupt is enabled.

Bit 14 – TAMPER Tamper Enable

Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Tamper Interrupt Enable bit, which enables the Tamper interrupt.

Value	Description
0	The Tamper interrupt it disabled.
1	The Tamper interrupt is enabled.

25.9.5 Interrupt Enable Set

Bit 15 – OVF Overflow Interrupt Enable

Bit 14 – TAMPER Tamper Enable

Bits 11:8 – ALARM[3:0] Alarm x Interrupt Enable

Bits 7:0 – PER[7:0] Periodic Interval x Enable