31.2.9.3 Single Error Corrected (FFLTSYN.DSERR)

When ECC is active (i.e. not OFF/Bypass) and a read from Flash memory results in an ECC Single Error Corrected (SEC), the FCR reports it via an interrupt (when SECCNT=0) since it is not a critical error. Data in the read buffer, prefetch buffer, or cache (depending on implementation) is correct and no further ECC events are generated for reads that hit the buffer as long as that data is in the buffer. See Section 2.5 for SEC on access to VSS pages for a device family that has an HSM option.

Each read of the flash that results in an SEC causes the FCR to set FFLTSYN.DSERR when SECCNT[] = 0. If the count in SECCNT is non-zero the FCR decrements it and does not set DSERR. The FCR does not reload SECCNT[] when it is zero. Software must write the desired count each time it services the SEC interrupt.

When Dynamic ECC is active, an SEC can be caused by a bit error in CTL. If this is the case, a DED and an SEC can be caused by the same read.