36.9.7 Host Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register.

This register is cleared by USB reset or when PEN[n] is zero.

Name:	INTENSET
Offset:	0x018
Reset:	0x0000
Property:	RW


Bit	15	14	13	12	11	10	9	8
							DDISC	DCONN
Access							RW	RW
Reset							0	0


Bit	7	6	5	4	3	2	1	0
	RAMACER	UPRSM	DNRSM	WAKEUP	RST	HSOF
Access	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0

Bit 9 – DDISC Device Disconnection Interrupt Enable

36.9.7 Host Interrupt Enable Set

Bit 9 – DDISC Device Disconnection Interrupt Enable

Bit 8 – DCONN Link Power Management Interrupt Enable

Bit 7 – RAMACER Ram Access Interrupt Enable

Bit 6 – UPRSM Upstream Resume fromthe device Interrupt Enable

Bit 5 – DNRSM DownStream to the Device Interrupt Enable

Bit 4 – WAKEUP Wake Up Interrupt Enable

Bit 3 – RST Bus Reset Interrupt Enable

Bit 2 – HSOF Host Start Of Frame Interrupt Enable