Clock Generation

As the host device in a synchronous communication interface, the USART in SPI Host mode must generate the interface clock to be shared with the client devices. The interface clock is generated using the fractional Baud Rate Generator, as described in The Fractional Baud Rate Generator.

Each Data bit is transmitted by pulling the data line high or low for one full clock period. The receiver samples each bit in the middle of the transmitter's hold period, as illustrated in the figure below. The timing scheme can be configured using the Inverted I/O Enable (INVEN) bit in the PORTx.PINnCTRL register and the Clock Phase (CPHA) bit in the USARTn.CTRLC register.

Figure 25-5. Data Transfer Timing Diagrams

The table below provides additional explanation for the figure above.

Table 25-2. Functionality of the INVEN and CPHA Bits
INVEN	CPHA	Leading Edge ⁽¹⁾	Trailing Edge ⁽¹⁾
0	0	Rising, sample	Falling, transmit
0	1	Rising, transmit	Falling, sample
1	0	Falling, sample	Rising, transmit
1	1	Falling, transmit	Rising, sample

Note:

The leading edge is the first clock edge of a clock cycle, while the trailing edge is the last clock edge of a clock cycle.