This bit field
controls the division factor from the peripheral clock (CLK_PER) to the ADC clock
(CLK_ADC). The generated frequency is fCLK_PER /
(PRESC+2)
| Value | Name | Description |
|---|
| 0x0 |
DIV2 |
CLK_PER
divided by 2 |
| 0x1 |
DIV3 |
CLK_PER
divided by 3 |
| 0x2 |
DIV4 |
CLK_PER
divided by 4 |
| 0x3 |
DIV5 |
CLK_PER
divided by 5 |
| 0x4 |
DIV6 |
CLK_PER
divided by 6 |
| 0x5 |
DIV7 |
CLK_PER
divided by 7 |
| 0x6 |
DIV8 |
CLK_PER
divided by 8 |
| 0x7 |
DIV9 |
CLK_PER
divided by 9 |
| 0x8 |
DIV10 |
CLK_PER
divided by 10 |
| 0x9 |
DIV11 |
CLK_PER
divided by 11 |
| 0xA |
DIV12 |
CLK_PER
divided by 12 |
| 0xB |
DIV13 |
CLK_PER
divided by 13 |
| 0xC |
DIV14 |
CLK_PER
divided by 14 |
| 0xD |
DIV15 |
CLK_PER
divided by 15 |
| 0xE |
DIV16 |
CLK_PER
divided by 16 |
| 0xF |
DIV17 |
CLK_PER
divided by 17 |
| 0x10 |
DIV18 |
CLK_PER divided by 18 |
| 0x11 |
DIV19 |
CLK_PER divided by 19 |
| 0x12 |
DIV20 |
CLK_PER divided by 20 |
| 0x13 |
DIV21 |
CLK_PER divided by 21 |
| 0x14 |
DIV22 |
CLK_PER divided by 22 |
| 0x15 |
DIV23 |
CLK_PER divided by 23 |
| 0x16 |
DIV24 |
CLK_PER divided by 24 |
| 0x17 |
DIV25 |
CLK_PER divided by 25 |
| 0x18 |
DIV26 |
CLK_PER divided by 26 |
| 0x19 |
DIV27 |
CLK_PER divided by 27 |
| 0x1A |
DIV28 |
CLK_PER divided by 28 |
| 0x1B |
DIV29 |
CLK_PER divided by 29 |
| 0x1C |
DIV30 |
CLK_PER divided by 30 |
| 0x1D |
DIV31 |
CLK_PER divided by 31 |
| 0x1E |
DIV32 |
CLK_PER divided by 32 |
| 0x1F |
- |
RESERVED |
