8.12 I/O Memory

All AVR16LA14/20/28/32 devices have their I/O and peripheral registers located in the I/O memory space. Refer to the Peripheral Address Map table for further details.

For compatibility with future devices, when writing to a register that contains reserved bits, those bits must be written as ‘0’. Reserved I/O memory addresses must never be written.

Single-Cycle I/O Registers

The I/O memory range from 0x00 to 0x3F can be accessed by single-cycle CPU instructions using the IN or OUT instructions.

The peripherals available in the single-cycle I/O registers are as follows:

  • VPORTx
    • Refer to the PORT I I/O Configuration chapter for further details
  • GPR
    • Refer to the GPR - General Purpose Register chapter for further details
  • CPU
    • Refer to the AVR CPU chapter for further details

The single-cycle I/O registers ranging from 0x00 to 0x1F (VPORTx and GPR) are also directly bit-accessible using the SBI or CBI instruction. In these single-cycle I/O registers, individual bits can be checked using the SBIS or SBIC instruction.

Refer to the Instruction Set Summary chapter for further details.