7 Entering Two-Wire Enhanced ICSP Mode

To use the Two-Wire PGEDx and PGECx pins for programming, they must be enabled. Note that any pair of programming pins available on a particular device may be used, however, they must be used as a pair. PGED1 must be used with PGEC1, and so on.

Note: If using the Four-Wire JTAG interface, the following procedure is not necessary.

The following steps are required to enter the Two-Wire Enhanced ICSP™ mode:

The MCLR pin is briefly driven high, then low.
A 32-bit key sequence is clocked into PGEDx.
The MCLR pin is then driven high within a specified period of time and held.

Refer to the AC/DC Characteristics and Timing Requirements for timing requirements.

The programming voltage applied to the MCLR pin is VIH, which is essentially VDD, in PIC32 devices. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P18 must elapse before presenting the key sequence on PGEDx.

The key sequence is a specific 32-bit pattern 0100 1101 0100 0011 0100 1000 0101 0000 (the acronym ‘MCHP’, in ASCII). The device will enter the Program/Verify mode only if the key sequence is valid. The MSb of the Most Significant nibble must be shifted in first.

Once the key sequence is complete, VIH must be applied to the MCLR pin and held at that level for as long as the Two-Wire Enhanced ICSP interface is to be maintained. An interval of at least time P19 and P7 must elapse before presenting data on PGEDx. Signals appearing on PGEDx before P7 has elapsed will not be interpreted as valid.

Upon successful entry, the programming operations documented in subsequent sections can be performed. While in Two-Wire Enhanced ICSP mode, all unused I/Os are placed in the high-impedance state.

Note: Entering the ICSP mode puts the device into a Reset state to prevent instruction execution. To release the Reset, the MCHP_DEASSERT_RST command must be issued.