22 Document Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Table 22-1. Document Revision History
Revision	Date	Section	Description
AB	11/2024	Appendix C: Device IDs	Updated Table with device IDs.
		Mask Values	Updated with Flash Memory Sizes (KB) in Table 18-1
		Flash Memory	Updated Table 5-1 with new Flash Memory address ranges for PIC32MZ W1
AA	07/2021	Device Configuration for PIC32MZ W1 Devices	Updated Table 19-6 with new physical address
Y	09/2020	Appendix C: Device IDs	Added Table with PIC32MZ W1 Wi-Fi® Connectivity Family Device ID
		Mask Values	Updated PIC32MZ W1 device information in Table 18-1
		Device Configuration for PIC32MZ W1 Devices	Added section
		Flash Memory	Updated section with PIC32MZ W1 information Added note that applies to the PIC32MZ W1 devices
		PIC32MZ W1 Power Requirements	Added section
X	11/2019	Algorithm	Updated Equation 18-1 with PIC32MKXXXXGPD/GPE/MCFXXX device information
		Mask Values	Updated PIC32MKXXXXGPD/GPE/MCFXXX device information in Table 18-1
		Theory	Added a new note that applies to PIC32MKXXXXGPD/GPE/MCFXXX devices
W	10/2018	Document	The following are the updates: Added note below Table 13-1 and Table 14-1 Moved content from Table C-13 to Table
V	07/2018	Appendix C: Device IDs	Removed references to PIC32MKXXXXMCM/GPL/GPKXXX and PIC32MKXXXXMCH/GPGXXX in Table Rearranged PIC32MKXXXX/MCM/ GPL/GPKXXX devices in Table Added PIC32MKXXXX- MCJ/GPH/GPGXXX devices in Table Added note reference to the revision ID has been from Table to Table
		Device Configuration	Renamed family name from PIC32MKXXXXXXG/H/K/L/MXX to PIC32MKXXXXXXH/G/J/K/L/MXX in Table 19-5
		Mask Values	Renamed PIC32MK0256/0512XXG/H to PIC32MK0256/0512XXH/G/J. Also, updated Device Configuration register mask values for PIC32MK0512/1024XXK/L/M and PIC32MK0512/1024XXH/G/J in Table 18-1
U	07/2017	Document	The following are the updates: Minor updates to text and formatting were incorporated throughout the document Updated the PIC32MK devices in Devices with Dual Flash Panel and Dual Boot Regions Updated Table 5-1, Table 18-1, Table 19-4 and Table Added Table 19-5
T	05/2017	Document	The following are the updates: Minor updates to text and formatting were incorporated throughout the document Updated Figure 4-1, Figure 4-2 and Figure 5-2 Updated Table 4-1, Table 4-2 and Table 20-1 Added Table
S	09/2016	Appendix C: Device IDs	Added Table through Table
S	09/2016	Document	The following are the updates: Updated Figure 4-1, Figure 4-5 and Figure 5-2 Updated Table 4-1, Table 4-2 and Table 21-1 Updated Note in 2-phase ICSP
R	04/2016	Table 21-1	Added parameters D112 (V_DD1V8) and D115 (I_DD1V8P)
		PIC32MX With V_BAT Pin Power PIC32MZ EC and PIC32MZ EF Power Requirements PIC32MZ DA Power Requirements PIC32MK Power Requirements Synchronization Synchronize (`Synchronize`) Pseudo Operation	Added section
		Document	The following are the updates: Updated Figure 4-1, Figure 4-4, Figure 4-5, Figure 5-2, Figure 16-1, Figure 16-2 Updated Table 4-1, Table 4-2, Table 5-1, Table 13-1 and Table 18-1 Updated PIC32MX Power Requirements Updated Four-Wire Interface Updated Two-Wire Interface Updated Note 1 in the Equation 18-1
Q	07/2015	Device Configuration	Updated Table 19-3 to include DEVCFG4
		Algorithm	Updated Equation 18-1
		Table 18-1	Updated to include DEVCFG4
		Initiating a Flash Row Write	Added section
		Document	Minor updates to text and formatting were incorporated throughout the document
P	10/2014	Device Configuration	Added Table 19-4
		Example of Checksum Calculation	Removed Table 18-4: Device IDs and Revision as this information is readily available in the current Family Silicon Errata
		Table 5-1 Table 18-1	Updated to include PIC32MK device information
		Document	Note: The revision history in this document intentionally skips from Revision N to Revision P to avoid confusing the uppercase letter ‘O’ with the number zero (0).
N	04/2014	Appendix C: Device IDs	The Revision ID and Silicon Revision column was updated and the following = devices were added to the Device IDs and Revision table (see Table ): PIC32MX170F256B→PIC32MX350F256H PIC32MX170F256D→PIC32MX350F256L PIC32MX270F256B→PIC32MX430F064H PIC32MX270F256D→PIC32MX430F064L PIC32MX330F064H→PIC32MX450F128H PIC32MX330F064L→PIC32MX450F128L PIC32MX350F128H→PIC32MX450F256H PIC32MX350F128L→PIC32MX450F256L
		Erasing the Device	Updated delay value in Step 5
		Two-Wire Interface	Updated Note 2 in Table 4-2
		Four-Wire Interface	Updated Note 2 in Table 4-1
M	09/2013	Device Configuration	Updated Device IDs and Revision in Table 19-4
		Algorithm	Removed the first sentence in the fourth paragraph
		Mask Values	Updated Device Configuration Register Mask Values in Table 18-1
		Quad Word Program (`QUAD_WORD_PROGRAM`) Command	Updated the Op code description in Table 17-17
		Without the PE	Added a new paragraph Updated Step 2, 3 and 5 in Table 13-1
		Downloading the Programming Executive (PE)	Updated Steps 1, 2, 3 and 5 in Table 11-1
		Flash Memory	Updated Code Memory Sizes and added Note 3 (see Table 5-1)
		Programming Overview Flash Memory Figure 9-1	Updated section
		Document	All references to MIPS Technologies Inc. and www.mips.com were updated to Imagination Technologies Limited and www.imgtec.com,respectively
L	01/2013	Device Configuration	Updated all addresses in DEVCFG locations (see Table 19-1 and Table 19-2) Added configuration word locations for PIC32MZEC family devices
		Command Format	Added Note 3 and Note 4 (see Table 17-2): `GET_CHECKSUM` `QUAD_WORD_PRGM`
		Flash Memory	Added the following new devices to the Code Memory Size table (see Table 5-1) and the Device IDs and Revision table (see Table ): PIC32MZ0256ECE064→PIC32MZ1024ECF064 PIC32MZ0256ECE100→PIC32MZ1024ECF100 PIC32MZ0256ECE124→PIC32MZ1024ECF124 PIC32MZ0256ECE144→PIC32MZ1024ECF144 PIC32MZ0256ECF064→PIC32MZ1024ECG064 PIC32MZ0256ECF100→PIC32MZ1024ECG100 PIC32MZ0256ECF124→PIC32MZ1024ECG124 PIC32MZ0256ECF144→PIC32MZ1024ECG144 PIC32MZ0512ECE064→PIC32MZ1024ECH064 PIC32MZ0512ECE100→PIC32MZ1024ECH100 PIC32MZ0512ECE124→PIC32MZ1024ECH124 PIC32MZ0512ECE144→PIC32MZ1024ECH144 PIC32MZ0512ECF064→PIC32MZ2048ECG064 PIC32MZ0512ECF100→PIC32MZ2048ECG100 PIC32MZ0512ECF124→PIC32MZ2048ECG124 PIC32MZ0512ECF144→PIC32MZ2048ECG144 PIC32MZ1024ECE064→PIC32MZ2048ECH064 PIC32MZ1024ECE100→PIC32MZ2048ECH100 PIC32MZ1024ECE124→PIC32MZ2048ECH124 PIC32MZ1024ECE144→PIC32MZ2048ECH144
		Mask Values	Updated Device Configuration Register Mask Values in Table 18-1
		PIC32MX Power Requirements Initiating a Flash Row Write Two-Wire ICSP EJTAG Rate Device Code Protection Bit (CP) Program Write Protection (PWP) Bits	Updated section
		Devices with Dual Flash Panel and Dual Boot Regions Get Checksum (`GET_CHECKSUM`) Command Quad Word Program (`QUAD_WORD_PROGRAM`) Command	Added section
		Document	All references to Test mode were updated to Programming mode throughout the document Minor updates to text and formatting were incorporated through the document
K	07/2012	AC/DC Characteristics and Timing Requirements	Removed parameter D112 Replaced Notes 1 and 2 with a new Note 1 Updated parameters D111, D113, D114, D031, D041, D080, D090, D012, D013, P11, P12 and P13
		ECR: EJTAG Control Register	Added register
		Device Code Protection Bit (CP)	Added a Note
		Flash Memory	Added the following new devices to the Code Memory Size table (see Table 5-1) and the Device IDs and Revision table (see Table ): PIC32MX420F032H→PIC32MX450F128 PIC32MX330F064H→PIC32MX440F256H PIC32MX330F064L→PIC32MX450F256H PIC32MX430F064H→PIC32MX450F256L PIC32MX430F064L→PIC32MX460F256L PIC32MX340F128H→PIC32MX340F512H PIC32MX340F128L→PIC32MX360F512H PIC32MX350F128H→PIC32MX370F512H PIC32MX350F128L→PIC32MX370F512L PIC32MX350F256H→PIC32MX440F512H PIC32MX350F256L→PIC32MX460F512L PIC32MX440F128H→PIC32MX470F512H PIC32MX440F128L→PIC32MX470F512L PIC32MX450F128H
		Completing the PIC32 Checksum Calculation	Updated the Checksum Calculation Process (see Completing the PIC32 Checksum Calculation)
		Calculating for “DCR” in the Checksum Formula	Updated the DCR value and Table 18-2
		Mask Values	Updated the mask values for all the PIC32MX1XX and the PIC32MX2XX devices, and DEVCFG3 for all devices in Table 18-1
		The PE Command Set	Added references to the Operand field throughout the section
		Programming Executive	Added a note regarding the PE location
		Verifying Memory without the PE	Updated Step 1 in Verify Device OP Codes (see Table 14-1)
		Without the PE	Updated Step 3 in Initiate Flash Row Write OP Codes (see Table 13-1)
		Two-Wire Interface	Updated step 11
		Entering Serial Execution Mode	Updated Figure 10-1
		PIC32MX Power Requirements	Added Note 2 to Connections for the On-chip Regulator (see Figure 4-2)
		Two-Wire Interface	Added Note 2 to the 2-wire Interface Pins tables (see Table 4-2)
		Four-Wire Interface	Added Note 2 to the 4-wire Interface Pins tables (see Table 4-1)
		Connecting to the Device Entering Two-Wire Enhanced ICSP Mode With the PE Four-Wire Interface Two-Wire Interface Program (`Program`) Command ETAP EJTAG Boot (`ETAP_EJTAGBOOT`) Command	Updated section
		Data Sizes	Added section
		Introduction	Updated with a list of all major topics in this document
		Document	Minor updates to text and formatting were incorporated through the document All occurrences of PGC and PGD were changed to: PGEC and PGED, respectively
J	08/2011	AC/DC Characteristics and Timing Requirements	The following changes were made to the AC/DC Characteristics and Timing Requirements (Table 21-1): Updated the Min. value for parameter D111 (V_DD) Added parameter D114 (I_PEAK) Removed parameters P2, P3, P4, P4A, P5, P8 and P10
		Mask Values	Updated the DEVCFG0 and DEVCFG1 values for All PIC32MX1XX and All PIC32MX2XX devices in Table 18-1
		Change CFG (`CHANGE_CFG`) Command	Added a note after the `CHANGE_CFG` response (see Figure 17-27)
		Program Cluster (`PROGRAM_CLUSTER`) Command	Updated the address and length descriptions in the `PROGRAM_CLUSTER` format (see Table 16-13)
		Get CRC (`GET_CRC`) Command	Added section
		Command Format	Updated the PE Command Set with the following commands and modified Note 2 (see Table 16-2): `PROGRAM_CLUSTER` `GET_DEVICEID` `CHANGE_CFG`
		Two-Wire Interface	Updated the MCLR signal in Two-Wire Exit Test Mode (see Figure 16-2)
		Erasing the Device	Updated the Erase Device block diagram (see Figure 9-1) Added a new step 4 to the process to erase a target device
		Entering Two-Wire Enhanced ICSP Mode	Updated the PGCx signal in Entering Enhanced ICSP Mode (see Figure 7-1)
		Flash Memory	Added the following new devices to the Code Memory Size table (see Table 5-1) and the Device IDs and Revision table (see Table ): PIC32MX130F064B PIC32MX130F064C PIC32MX130F064D PIC32MX150F128B PIC32MX150F128C PIC32MX150F128D PIC32MX230F064B PIC32MX230F064C PIC32MX230F064D PIC32MX250F128B PIC32MX250F128C PIC32MX250F128D Added Row Size and Page Size columns to the Code Memory Size table (see Table 5-1)
		Two-Wire Interface	Removed the column, Programmer Pin Name, from the 2-Wire Interface Pins table and updated the Pin Type for MCLR (see Table 4-2)
		Programming Overview	Updated the fourth paragraph
		Document	Note: The revision history in this document, intentionally skips from Revision H to Revision J to avoid confusing the uppercase letter “I” (EY) with the lowercase letter “l” (EL). This revision includes the following updates: Minor updates to text and formatting were incorporated throughout the document All occurrences of VCORE/VCAP have been changed to VCAP Removed Appendix C: “Flash Program Memory Data Sheet Clarification”
H	04/2011	Appendix A: PIC32 Flash Memory Map	Added a note to the Flash Memory Map (see Figure )
		MCHP Status Value Register	Added the NVMERR bit to the MCHP Status Value table
		Configuration Memory and Device ID	Removed Table 18-1 and updated Table 18-2: DEVID Summary as Table 18-1 The following Silicon Revision and Revision ID are added to Table 18-4: 0x5- B6 Revision 0x1- A1 Revision
		Checksum Values while Device is Code-Protected	Added section
		Appendix C: Device IDs	The following devices were added in Table : PIC32MX110F016B PIC32MX110F016C PIC32MX110F016D PIC32MX120F032B PIC32MX120F032C PIC32MX120F032D PIC32MX210F016B PIC32MX210F016C PIC32MX210F016D PIC32MX220F032B PIC32MX220F032C PIC32MX220F032D
		Document	Updates to formatting and minor typographical changes have been incorporated throughout the document The following rows were added to Table 17-1: PIC32MX1X0 PIC32MX2X0 Removed Register 18-1 through Register 18-5. Removed Table 17-2 Removed Section 17.5 “Checksum for PIC32 Devices” and its sub sections The Flash Program Memory Write-Protect Range stable was removed (formerly Table 18-4) Added DEVCFG Locations for PIC32MX1X0 and PIC32MX20X Devices Only (see Table 18-3) Added Appendix C: Flash Program Memory Data Sheet Clarification
G	08/2010	Downloading the Programming Executive (PE)	Updated step 3 in Table 11-1 (Downloading the PE)
G	08/2010	Document	Minor corrections to formatting changes throughout the document
F	04/2010	Appendix C: Device IDs	Added the following devices: PIC32MX534F064H PIC32MX534F064L PIC32MX564F064H PIC32MX564F064L PIC32MX564F128H PIC32MX564F128L PIC32MX575F256L PIC32MX664F064H PIC32MX664F064L PIC32MX664F128H PIC32MX664F128L PIC32MX675F256H PIC32MX675F256L PIC32MX695F512H PIC32MX605F512L PIC32MX764F128H PIC32MX764F128L PIC32MX775F256H PIC32MX775F256L PIC32MX775F512H PIC32MX775F512L
		Initiating a Page Erase	Updated the Initiate Flash Row Write Op Codes and instructions (see steps 4, 5 and 6 in Table 13-1)
		2-phase ICSP	Updated the note
		Programming Overview	Updated the PIC32MX family data sheet references in the fourth paragraph
		Document	This version of the document includes the following additions and updates: The following global bit name changes were made: NVMWR renamed as WR NVMWREN renamed as WREN NVMERR renamed as WRERR FVBUSIO renamed as FVBUSONIO FUPLLEN renamed as UPLLEN FUPLLIDIV renamed as UPLLIDIV POSCMD renamed as POSCMOD
E	07/2009	Appendix B: HEX File Format	Added chapter
		Checksum	Added Notes 1-3 and the following bits to the DEVCFG - Device Configuration Word Summary and the DEVCFG3: Device Configuration Word 3 (see Table 18-1 and Register): FVBUSIO FUSBIDIO FCANIO FETHIO FMIIEN FPBDIV[1:0] FJTAGEN Updated the DEVID Summary (see Table 18-1)
		Programming Executive	Added the following devices to Table 17-5: PIC32MX565F256H PIC32MX575F512H PIC32MX575F512L PIC32MX675F512H PIC32MX675F512L PIC32MX795F512H PIC32MX795F512L Updated address values in Table 17-2 Added the following devices to Table : PIC32MX565F256H PIC32MX575F512H PIC32MX675F512H PIC32MX795F512H PIC32MX575F512L PIC32MX675F512L PIC32MX795F512L
		Initiating a Page Erase	The following instructions in Table 13-1 were updated: Seventh, ninth and eleventh instructions in Step 1 All instructions in Step 2 First instruction in Step 3 Third instruction in Step 4
		Downloading the Programming Executive (PE)	Updated Step 7 of Table 11-1 to clarify repeat of the last instruction in the step
		Entering Two-Wire Enhanced ICSP Mode	Updated MCLR pulse line to show active-high (P20) in Figure 7-1
		Document	Minor changes to style and formatting have been incorporated throughout the document Added the following devices: PIC32MX565F256H PIC32MX575F512H PIC32MX675F512H PIC32MX795F512H PIC32MX575F512L PIC32MX675F512L PIC32MX795F512L Updated the DEVID Summary (see Table 18-1) Updated ICESEL bit description and added the FJTAGEN bit in DEVCFG0: Device Configuration Word 0 (see Register 16-1) Updated DEVID: Device and Revision ID register Added Device IDs and Revision table (Table 18-4) Added MCLR High Time (parameter P20) to Table 20-1
D	05/2008	Document	Update records for this revision are not available
C	04/2008	Document	Update records for this revision are not available
B	02/2008	Document	Update records for this revision are not available
A	08/2007	Document	Initial Revision