21 AC/DC Characteristics and Timing Requirements

Table 21-1. AC/DC Characteristics and Timing Requirements
Parameter Number	Symbol	Characteristic	Min.	Max.	Units	Conditions
Standard Operating Conditions Operating Temperature: 0ºC to +70ºC. Programming at +25ºC is recommended.
D111	V_DDIO	Supply voltage during programming	—	—	V	⁽¹⁾
D112a	V`DDCORE`	Core power supply voltage during programming	—	—	V	⁽¹⁾
D112b	V`DDR1V8`	DDR SDRAM supply voltage during programming	—	—	V	⁽¹⁾
D113	I`DDP`	Supply current during programming	—	—	mA	⁽¹⁾
D114	I`PEAK`	Instantaneous peak current during start-up	—	—	mA	⁽¹⁾
D115a	I`DDCORE`	Core power supply current during programming	—	—	mA	⁽¹⁾
D115b	I`DDR1V8P`	DDR SDRAM supply current during programming	—	—	mA	⁽¹⁾
D116	V`DDVBAT`	V_BAT supply voltage during programming	—	—	V	⁽¹⁾
D117	I`DDVBAT`	VBAT supply current during programming	—	—	mA	⁽¹⁾
D031	V`IL`	Input low voltage	—	—	V	⁽¹⁾
D041	V`IH`	Input high voltage	—	—	V	⁽¹⁾
D080	V`OL`	Output low voltage	—	—	V	⁽¹⁾
D090	V`OH`	Output high voltage	—	—	V	⁽¹⁾
D012	C`IO`	Capacitive loading on I/O pin (PGEDx)	—	—	pF	⁽¹⁾
D013	C`F`	Filter capacitor value on V_CAP	—	—	mF	⁽¹⁾
P1	T`PGC`	Serial clock (PGECx) period	100	—	ns	—
P1A	T`PGCL`	Serial clock (PGECx) low time	40	—	ns	—
P1B	T`PGCH`	Serial clock (PGECx) high time	40	—	ns	—
P6	T`SET2`	V_DD ↑ setup time to MCLR ↑	100	—	ns	—
P7	T`HLD2`	Input data hold time from MCLR ↑	500	—	ns	—
P9a	T`DLY4`	PE command processing time	40	—	ms	—
P9b	T`DLY5`	Delay between PGEDx ↓ by the PE to PGEDx released by the PE	15	—	ms	—
P11	T`DLY7`	Chip erase time	—	—	ms	⁽¹⁾
P12	T`DLY8`	Page erase time	—	—	ms	⁽¹⁾
P13	T`DLY9`	Row programming time	—	—	ms	⁽¹⁾
P14	T`R`	MCLR rise time to enter ICSP™ mode	—	1.0	ms	—
P15	T`VALID`	Data out valid from PGECx ↑	10	—	ns	—
P16	T`DLY8`	Delay between last PGECx ↓ and MCLR ↓	0	—	s	—
P17	T`HLD3`	MCLR ↓ to V_DD ↓	—	100	ns	—
P18	T`KEY1`	Delay from first MCLR ↓ to first PGECx ↑ for key sequence on PGEDx	40	—	ns	—
P19	T`KEY2`	Delay from last PGECx ↓ for key Sequence on PGEDx to second MCLR ↑	40	—	ns	—
P20	T`MCLRH`	MCLR high time	—	500	µs	—
Note: For the minimum and maximum values for this parameter, refer to the Electrical Characteristics chapter in the specific device data sheet.

Standard Operating Conditions

Operating Temperature: 0ºC to +70ºC. Programming at +25ºC is recommended.

D111

V_DDIO

Supply voltage during programming

—

V

⁽¹⁾

D112a

VDDCORE

Core power supply voltage during programming

—

V

⁽¹⁾

D112b

VDDR1V8

DDR SDRAM supply voltage during programming

—

V

⁽¹⁾

D113

IDDP

Supply current during programming

—

mA

⁽¹⁾

D114

IPEAK

Instantaneous peak current during start-up

—

mA

⁽¹⁾

D115a

IDDCORE

Core power supply current during programming

—

mA

⁽¹⁾

D115b

IDDR1V8P

DDR SDRAM supply current during programming

—

mA

⁽¹⁾

D116

VDDVBAT

V_BAT supply voltage during programming

—

V

⁽¹⁾

D117

IDDVBAT

VBAT supply current during programming

—

mA

⁽¹⁾

D031

VIL

Input low voltage

—

V

⁽¹⁾

D041

VIH

Input high voltage

—

V

⁽¹⁾

D080

VOL

Output low voltage

—

V

⁽¹⁾

D090

VOH

Output high voltage

—

V

⁽¹⁾

D012

CIO

Capacitive loading on I/O pin (PGEDx)

—

pF

⁽¹⁾

D013

CF

Filter capacitor value on V_CAP

—

mF

⁽¹⁾

P1

TPGC

Serial clock (PGECx) period

100

—

ns

—

P1A

TPGCL

Serial clock (PGECx) low time

40

—

ns

—

P1B

TPGCH

Serial clock (PGECx) high time

40

—

ns

—

P6

TSET2

V_DD ↑ setup time to MCLR ↑

100

—

ns

—

P7

THLD2

Input data hold time from MCLR ↑

500

—

ns

—

P9a

TDLY4

PE command processing time

40

—

ms

—

P9b

TDLY5

Delay between PGEDx ↓ by the PE to PGEDx released by the PE

15

—

ms

—

P11

TDLY7

Chip erase time

—

ms

⁽¹⁾

P12

TDLY8

Page erase time

—

ms

⁽¹⁾

P13

TDLY9

Row programming time

—

ms

⁽¹⁾

P14

TR

MCLR rise time to enter ICSP™ mode

—

1.0

ms

—

P15

TVALID

Data out valid from PGECx ↑

10

—

ns

—

P16

TDLY8

Delay between last PGECx ↓ and MCLR ↓

0

—

s

—

P17

THLD3

MCLR ↓ to V_DD ↓

—

100

ns

—

P18

TKEY1

Delay from first MCLR ↓ to first PGECx ↑ for key sequence on PGEDx

40

—

ns

—

P19

TKEY2

Delay from last PGECx ↓ for key Sequence on PGEDx to second MCLR ↑

40

—

ns

—

P20

TMCLRH

MCLR high time

—

500

µs

—

Note:

For the minimum and maximum values for this parameter, refer to the Electrical Characteristics chapter in the specific device data sheet.