30.8.5 Advanced Features

SleepWalking is the capability for a device to temporarily wake up clocks for a peripheral to perform a task without waking up the CPU from Standby sleep mode. At the end of the sleepwalking task, the device can either be awakened by an interrupt (from a peripheral involved in SleepWalking) or enter again into Standby Sleep mode.

In Standby when Sleepwalking is ongoing:

• All the power domains are turned on including PDRAM power domain
• Low-power mode of the regulators is not activated during sleepwalking

As shown in the following figure, total wake-up time depends on:

• Latency due to Reference and Regulator effect.

  As example, if the device is in LV Standby sleep mode using the voltage regulators for VDDCORE_SW_PD (VREGSWn, n = 0,1) in low-power mode, the voltage level is lower than the one used in Active mode. When the device wakesup, it takes a certain amount of time for the main regulators (VREGSWn and VREGRAM) to transition to the voltage level corresponding to Active mode, causing additional wake-up time.

• Latency due to Power Domain Gating:

  Usually, wake-up time is measured with the assumption that the power domains are already in active state. When using Power Domain Gating, changing a power domain from OFF to active state will take a certain time, refer to Electrical Characteristics. If all power domains were already in active state in Standby Sleep mode, this latency is zero.

• Latency due to the CPU clock source wake-up time.
• Latency due to the NVM wake-up time from deep power-down mode.